public static void GenerateFloatingPointCores()
{
var ise = ISEDetector.DetectMostRecentISEInstallation();
DesignContext.Reset();
var fpu = new FPUWrapper(ise.VersionTag);
DesignContext.Instance.Elaborate();
var fpga = new XC6VLX240T_FF1156();
fpga.SpeedGrade = ESpeedGrade._2;
fpga.TopLevelComponent = fpu;
var proj = fpga.Synthesize("c:\\temp\\fputest", "fpu", null,
EFlowStep.HDLGen | EFlowStep.IPCores);
var flow = proj.ConfigureFlow(fpu);
flow.TRCE.ReportUnconstrainedPaths = true;
flow.Start(
EFlowStep.XST |
EFlowStep.NGDBuild |
EFlowStep.Map |
EFlowStep.PAR |
EFlowStep.TRCE);
proj.AwaitRunningToolsToFinish();
PerformanceRecord designRec;
ResourceRecord deviceRec;
flow.ParseResourceRecords(out designRec, out deviceRec);
}
public static void GenerateFloatingPointCores()
{
var ise = ISEDetector.DetectMostRecentISEInstallation();
DesignContext.Reset();
var fpu = new FPUWrapper(ise.VersionTag);
DesignContext.Instance.Elaborate();
var fpga = new XC6VLX240T_FF1156();
fpga.SpeedGrade = ESpeedGrade._2;
fpga.TopLevelComponent = fpu;
var proj = fpga.Synthesize("c:\\temp\\fputest", "fpu", null,
EFlowStep.HDLGen | EFlowStep.IPCores);
var flow = proj.ConfigureFlow(fpu);
flow.TRCE.ReportUnconstrainedPaths = true;
flow.Start(
EFlowStep.XST |
EFlowStep.NGDBuild |
EFlowStep.Map |
EFlowStep.PAR |
EFlowStep.TRCE);
proj.AwaitRunningToolsToFinish();
PerformanceRecord designRec;
ResourceRecord deviceRec;
flow.ParseResourceRecords(out designRec, out deviceRec);
}
