private void ResetReadAddresses() { for (int j = 0; j < write_regs.Length; j++) { Mu2e_Register.WriteReg(0x0, ref write_regs[j], ref febClient.client); //Set the read pointers back to 0 } }
public ROOTNET.NTH1I[] GetHistogram(uint channel, byte binning) { //Get the registers for the requested channel GetRegisters(channel); //Get the read/write addresses which are important for starting and reading the histograms uint[,] channels = AFE_ChannelAddresses(channel); //0x60 uint histCntrl_Dark_Base = 0x60 + (uint)Ext_mode + channels[0, 4]; // This turns on the histogramming with the defined mode //binning should only be 1, 2, 4, or 8, since those are the only supported histogram bin widths switch (binning) { case 1: histCntrl_Dark_Base += 0x0; break; case 2: histCntrl_Dark_Base += 0x500; break; case 4: histCntrl_Dark_Base += 0xA00; break; case 8: histCntrl_Dark_Base += 0xF00; break; default: histCntrl_Dark_Base += 0x0; break; } //Get the registers specific to the requested channel SetRegisters(); //Start the histogramming and wait for it to finish (very quick) Mu2e_Register.WriteReg(histCntrl_Dark_Base, ref histo_controls[0], ref febClient.client); System.Threading.Thread.Sleep(accumulation_interval + 50); //small bit of time buffer added to the interval //Get and unpack the data UInt32[][] histogramBinContents = ParseData(ReceiveData(channel)); //Fill the histograms ROOTNET.NTH1I[] histo = new ROOTNET.NTH1I[2]; for (uint i = 0; i < 2; i++) { histo[i] = new ROOTNET.NTH1I("Ch" + channels[i, 3].ToString(), channels[i, 3].ToString(), 512, 0, binning * 512); for (uint binIndex = 0; binIndex < histogramBinContents[i].Length; binIndex++) { histo[i].SetBinContent((int)binIndex, histogramBinContents[i][binIndex]); } histo[i].GetXaxis().SetTitle("ADC"); histo[i].GetYaxis().SetTitle("N"); } //Return the histograms return(histo); }
private void SetRegisters() { for (int i = 1; i < histo_controls.Length; i++) { Mu2e_Register.WriteReg(accumulation_interval, ref histo_controls[i], ref febClient.client); //Set the accumulation interval } ResetReadAddresses(); }
public void SetAccumulation_Interval(ushort value) { accumulation_interval = value; for (int i = 1; i < histo_controls.Length; i++) { Mu2e_Register.WriteReg(accumulation_interval, ref histo_controls[i], ref febClient.client); //if we update the accumulation interval in the class, we need to update the registers on the FEB } }
public bool ReadCMB_SN(int FPGAnum, int CMB_num, out string CMB_ROM) { CMB_ROM = ""; try { if (_ClientOpen && FPGAnum < 4) { //CMB_set.fpga_index = Convert.ToUInt16(FPGAnum); //CMB_cmnd.fpga_index = Convert.ToUInt16(FPGAnum); //CMB_read.fpga_index = Convert.ToUInt16(FPGAnum); //addr25 Mu2e_Register.FindAddrFPGA(0x25, (uint)FPGAnum, ref this.arrReg, out Mu2e_Register CMB_set); //addr24 Mu2e_Register.FindAddrFPGA(0x24, (uint)FPGAnum, ref this.arrReg, out Mu2e_Register CMB_cmnd); //addr26 Mu2e_Register.FindAddrFPGA(0x26, (uint)FPGAnum, ref this.arrReg, out Mu2e_Register CMB_read); switch (CMB_num) { case 0: Mu2e_Register.WriteReg(1, ref CMB_set, ref this.client); break; case 1: Mu2e_Register.WriteReg(2, ref CMB_set, ref this.client); break; case 2: Mu2e_Register.WriteReg(4, ref CMB_set, ref this.client); break; case 3: Mu2e_Register.WriteReg(8, ref CMB_set, ref this.client); break; default: Mu2e_Register.WriteReg(1, ref CMB_set, ref this.client); break; } Mu2e_Register.WriteReg(0x200, ref CMB_cmnd, ref this.client); SendStr("rdi 26"); //This only reads the first FPGA, is this intended? ReadStr(out string t, out int rt); CMB_ROM = t; return(true); } else { return(false); } } catch { return(false); } }
public ROOTNET.NTH1I[] GetHistogram(uint channel, string suffix = "") { channel %= 8; //requested channel mod 8 (since each AFE only cares about the 8 channels connected to it) SetRegisters(); //Preps the FEB (re-sets accumulation interval and resets the read pointers) uint histCntrl_Dark_Base = 0x60 + (uint)Ext_mode + channel; // This is the "on" command for the histogramming and setting for gated histograms and the channel requested //Start the histogramming and wait for it to finish (very quick) Mu2e_Register.WriteReg(histCntrl_Dark_Base, ref histo_controls[0], ref febClient.client); System.Threading.Thread.Sleep(accumulation_interval + 250); //small bit of time buffer added to the interval //Get and unpack the data UInt32[][] histogramBinContents = ParseData(ReceiveData(channel)); //Fill the histograms ROOTNET.NTH1I[] histo = new ROOTNET.NTH1I[read_addrs.Length]; for (uint i = 0; i < read_addrs.Length; i++) { try { histo[i] = new ROOTNET.NTH1I("Ch" + ((8 * i) + channel).ToString() + suffix, ((8 * i) + channel).ToString(), num_bins, 0, num_bins); //First bin is underflow, last bin is overflow for (uint binIndex = 0; binIndex < histogramBinContents[i].Length; binIndex++) { histo[i].SetBinContent((int)binIndex + 1, histogramBinContents[i][binIndex]); } histo[i].GetXaxis().SetTitle("ADC"); histo[i].GetYaxis().SetTitle("N"); } catch (NullReferenceException) { //leave it as an empty histogram histo[i].GetXaxis().SetTitle("ADC"); histo[i].GetYaxis().SetTitle("N"); } } //Return the histograms return(histo); }
private void SetRegisters() { Mu2e_Register.WriteReg(accumulation_interval, ref histo_controls[1], ref febClient.client); //Set the accumulation interval Mu2e_Register.WriteReg(0x0, ref histo_controls[2], ref febClient.client); //Set the read pointers back to 0 Mu2e_Register.WriteReg(0x0, ref histo_controls[3], ref febClient.client); //Set the read pointers back to 0 }
public void SetAccumulation_interval(ushort value) { accumulation_interval = value; Mu2e_Register.WriteReg(accumulation_interval, ref histo_controls[1], ref febClient.client); //if we update the accumulation interval in the class, we need to update the register on the FEB }
public bool ReadCMB_SN(int FPGAnum, int CMB_num, out string CMB_ROM) { CMB_ROM = ""; try { if (_ClientOpen) { Mu2e_Register CMB_set; //addr25 Mu2e_Register.FindAddr(0x25, ref this.arrReg, out CMB_set); Mu2e_Register CMB_cmnd; //addr24 Mu2e_Register.FindAddr(0x24, ref this.arrReg, out CMB_cmnd); Mu2e_Register CMB_read; //addr26 Mu2e_Register.FindAddr(0x26, ref this.arrReg, out CMB_read); try { if (FPGAnum < 4) { CMB_set.fpga_index = Convert.ToUInt16(FPGAnum); CMB_cmnd.fpga_index = Convert.ToUInt16(FPGAnum); CMB_read.fpga_index = Convert.ToUInt16(FPGAnum); } } catch { } switch (CMB_num) { case 0: Mu2e_Register.WriteReg(1, ref CMB_set, ref this.client); break; case 1: Mu2e_Register.WriteReg(2, ref CMB_set, ref this.client); break; case 2: Mu2e_Register.WriteReg(4, ref CMB_set, ref this.client); break; case 3: Mu2e_Register.WriteReg(8, ref CMB_set, ref this.client); break; default: Mu2e_Register.WriteReg(1, ref CMB_set, ref this.client); break; } Mu2e_Register.WriteReg(0x200, ref CMB_cmnd, ref this.client); SendStr("rdi 26"); string t = ""; int rt = 0; ReadStr(out t, out rt); CMB_ROM = t; return(true); } else { return(false); } } catch { return(false); } }