static Stat()
{
for (uint i = 0; i < procs.Length; i++)
{
procs[i] = new ProcStat();
}
for (uint i = 0; i < mctrls.Length; i++)
{
mctrls[i] = new MemCtrlStat(i);
}
for (uint i = 0; i < busses.Length; i++)
{
busses[i] = new BusStat(i);
}
for (uint c = 0; c < Config.mem.channel_max; c++)
{
scheds[c] = new MemSchedStat();
for (uint r = 0; r < Config.mem.rank_max; r++)
{
for (uint b = 0; b < 8; b++)
{
banks[c, r, b] = new BankStat(c, r, b);
}
}
}
}
private void issue_cmd(Cmd cmd)
{
MemAddr addr = cmd.addr;
List <Cmd> cmd_q = cmdqs[addr.rid, addr.bid];
Dbg.Assert(cmd == cmd_q[0]);
cmd_q.RemoveAt(0);
BankStat bank_stat = Stat.banks[addr.cid, addr.rid, addr.bid];
BusStat bus_stat = Stat.busses[addr.cid];
//writeback mode stats
if (wb_mode)
{
if (cmd.type == Cmd.TypeEnum.READ)
{
rds_per_wb_mode++;
}
else if (cmd.type == Cmd.TypeEnum.WRITE)
{
wbs_per_wb_mode++;
}
}
//string dbg;
switch (cmd.type)
{
case Cmd.TypeEnum.ACTIVATE:
activate(addr);
/*dbg = String.Format("@{0,6} DRAM ACTI: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}",
* cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/
//stats
bank_stat.cmd_activate.Collect();
bank_stat.utilization.Collect(timing.tRCD);
//shadow row-buffer id
meta_mctrl.sched.count_queueing(cmd, pid_rowid_per_procrankbank[addr.rid, addr.bid]);
shadow_rowid_per_procrankbank[cmd.pid, addr.rid, addr.bid] = addr.rowid;
rowid_per_procrankbank[addr.rid, addr.bid] = addr.rowid;
pid_rowid_per_procrankbank[addr.rid, addr.bid] = cmd.req.pid;
break;
case Cmd.TypeEnum.PRECHARGE:
precharge(addr);
/*dbg = String.Format("@{0,6} DRAM PREC: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}",
* cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/
//stats
bank_stat.cmd_precharge.Collect();
bank_stat.utilization.Collect(timing.tRP);
break;
case Cmd.TypeEnum.READ:
read(addr, cmd.req.pid);
/*dbg = String.Format("@{0,6} DRAM READ: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}",
* cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/
//writeback mode
if (wb_mode && cmd.is_drain)
{
Dbg.Assert(reads_to_drain > 0);
reads_to_drain--;
}
//stats
bank_stat.cmd_read.Collect();
bank_stat.utilization.Collect(timing.tCL);
bus_stat.access.Collect();
bus_stat.utilization.Collect(timing.tBL);
// Console.Write("HERE\n");
meta_mctrl.sched.bus_interference_count(cmd);
break;
case Cmd.TypeEnum.WRITE:
write(addr, cmd.req.pid);
//writeback mode
if (!wb_mode && cmd.is_drain)
{
Dbg.Assert(writes_to_drain > 0);
writes_to_drain--;
}
else
{
mwbmode.issued_write_cmd(cmd);
}
//stats
bank_stat.cmd_write.Collect();
bank_stat.utilization.Collect(timing.tCL);
bus_stat.access.Collect();
bus_stat.utilization.Collect(timing.tBL);
break;
default:
//should never get here
throw new System.Exception("DRAM: Invalid Cmd.");
}
//Debug.WriteLine(dbg);
}
private void issue_cmd(Cmd cmd)
{
MemAddr addr = cmd.addr;
/*
* if (cid == 0 && wb_mode) {
* Console.Write("@{0}\t", cycles - ts_start_wbmode);
* for (uint b = 0; b < addr.bid; b++) {
* Console.Write("{0,4}", "-");
* }
* Console.Write("{0,4}", cmd.type.ToString()[0]);
* for (uint b = addr.bid; b < bmax; b++) {
* Console.Write("{0,4}", "-");
* }
* Console.WriteLine();
* }
*/
List <Cmd> cmd_q = cmdqs[addr.rid, addr.bid];
Dbg.Assert(cmd == cmd_q[0]);
cmd_q.RemoveAt(0);
BankStat bank_stat = Stat.banks2[addr.cid, addr.rid, addr.bid];
BusStat bus_stat = Stat.busses2[addr.cid];
//writeback mode stats
if (wb_mode)
{
if (cmd.type == Cmd.TypeEnum.READ)
{
rds_per_wb_mode++;
}
else if (cmd.type == Cmd.TypeEnum.WRITE)
{
wbs_per_wb_mode++;
}
}
//string dbg;
switch (cmd.type)
{
case Cmd.TypeEnum.ACTIVATE:
activate(addr);
/*dbg = String.Format("@{0,6} DRAM ACTI: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}",
* cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/
//stats
bank_stat.cmd_activate.Collect();
bank_stat.utilization.Collect(timing.tRCD);
//shadow row-buffer id
shadow_rowid_per_procrankbank[cmd.pid, addr.rid, addr.bid] = addr.rowid;
break;
case Cmd.TypeEnum.PRECHARGE:
precharge(addr);
/*dbg = String.Format("@{0,6} DRAM PREC: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}",
* cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/
//stats
bank_stat.cmd_precharge.Collect();
bank_stat.utilization.Collect(timing.tRP);
break;
case Cmd.TypeEnum.READ:
read(addr);
if (Config.proc.cache_insertion_policy == "PFA")
{
Measurement.Dram_bus_conflict_reset(cmd.req.pid);
}
/*dbg = String.Format("@{0,6} DRAM READ: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}",
* cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/
//writeback mode
if (wb_mode && cmd.is_drain)
{
Dbg.Assert(reads_to_drain > 0);
reads_to_drain--;
}
//stats
bank_stat.cmd_read.Collect();
bank_stat.utilization.Collect(timing.tCL);
bus_stat.access.Collect();
bus_stat.utilization.Collect(timing.tBL);
break;
case Cmd.TypeEnum.WRITE:
write(addr);
if (Config.proc.cache_insertion_policy == "PFA")
{
Measurement.Dram_bus_conflict_reset(cmd.req.pid);
}
/*dbg = String.Format("@{0,6} DRAM WRTE: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}",
* cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/
//writeback mode
if (!wb_mode && cmd.is_drain)
{
Dbg.Assert(writes_to_drain > 0);
writes_to_drain--;
}
else
{
mwbmode.issued_write_cmd(cmd);
}
//stats
bank_stat.cmd_write.Collect();
bank_stat.utilization.Collect(timing.tCL);
bus_stat.access.Collect();
bus_stat.utilization.Collect(timing.tBL);
break;
default:
//should never get here
throw new System.Exception("DRAM: Invalid Cmd.");
}
//Debug.WriteLine(dbg);
}
static Stat()
{
for (uint i = 0; i < procs.Length; i++)
procs[i] = new ProcStat();
for (uint i = 0; i < mctrls.Length; i++)
mctrls[i] = new MemCtrlStat(i);
for (uint i = 0; i < busses.Length; i++)
busses[i] = new BusStat(i);
for (uint c = 0; c < Config.mem.channel_max; c++) {
scheds[c] = new MemSchedStat();
for (uint r = 0; r < Config.mem.rank_max; r++) {
for (uint b = 0; b < 8; b++) {
banks[c, r, b] = new BankStat(c, r, b);
}
}
}
}
