private static CPUID[][] GroupThreadsByCore(IEnumerable <CPUID> threads)
{
SortedDictionary <uint, List <CPUID> > cores =
new SortedDictionary <uint, List <CPUID> >();
foreach (CPUID thread in threads)
{
List <CPUID> coreList;
cores.TryGetValue(thread.CoreId, out coreList);
if (coreList == null)
{
coreList = new List <CPUID>();
cores.Add(thread.CoreId, coreList);
}
coreList.Add(thread);
}
CPUID[][] coreThreads = new CPUID[cores.Count][];
int index = 0;
foreach (List <CPUID> list in cores.Values)
{
coreThreads[index] = list.ToArray();
index++;
}
return(coreThreads);
}
public CPULoad(CPUID[][] cpuid)
{
this.cpuid = cpuid;
this.coreLoads = new float[cpuid.Length];
this.totalLoad = 0;
try {
GetTimes(out idleTimes, out totalTimes);
} catch (Exception) {
this.idleTimes = null;
this.totalTimes = null;
}
if (idleTimes != null)
available = true;
}
public AMDCPU(int processorIndex, CPUID[][] cpuid, ISettings settings)
: base(processorIndex, cpuid, settings)
{
this.microarchitecture = Microarchitecture.Unknown;
System.Console.WriteLine(this.family);
switch (this.family)
{
case 0xC:
this.microarchitecture = Microarchitecture.K10;
break;
case 0xE:
this.microarchitecture = Microarchitecture.Bobcat;
break;
case 0x10:
switch (this.model)
{
case 0x2:
this.microarchitecture = Microarchitecture.Jaguar;
break;
case 0x3:
this.microarchitecture = Microarchitecture.Puma;
break;
}
break;
case 0x15:
switch (this.model)
{
case 0x1:
this.microarchitecture = Microarchitecture.Bulldozer;
break;
case 0x2:
this.microarchitecture = Microarchitecture.Piledriver;
break;
case 0x3:
this.microarchitecture = Microarchitecture.Steamroller;
break;
case 0x4:
this.microarchitecture = Microarchitecture.Excavator;
break;
}
break;
}
}
private static CPUID[][] GetProcessorThreads()
{
List <CPUID> threads = new List <CPUID>();
for (int i = 0; i < 64; i++)
{
try {
threads.Add(new CPUID(i));
} catch (ArgumentOutOfRangeException) { }
}
SortedDictionary <uint, List <CPUID> > processors =
new SortedDictionary <uint, List <CPUID> >();
foreach (CPUID thread in threads)
{
List <CPUID> list;
processors.TryGetValue(thread.ProcessorId, out list);
if (list == null)
{
list = new List <CPUID>();
processors.Add(thread.ProcessorId, list);
}
list.Add(thread);
}
CPUID[][] processorThreads = new CPUID[processors.Count][];
int index = 0;
foreach (List <CPUID> list in processors.Values)
{
processorThreads[index] = list.ToArray();
index++;
}
return(processorThreads);
}
private static CPUID[][] GroupThreadsByCore(IEnumerable<CPUID> threads)
{
SortedDictionary<uint, List<CPUID>> cores =
new SortedDictionary<uint, List<CPUID>>();
foreach (CPUID thread in threads) {
List<CPUID> coreList;
cores.TryGetValue(thread.CoreId, out coreList);
if (coreList == null) {
coreList = new List<CPUID>();
cores.Add(thread.CoreId, coreList);
}
coreList.Add(thread);
}
CPUID[][] coreThreads = new CPUID[cores.Count][];
int index = 0;
foreach (List<CPUID> list in cores.Values) {
coreThreads[index] = list.ToArray();
index++;
}
return coreThreads;
}
private static CPUID[][] GetProcessorThreads()
{
List<CPUID> threads = new List<CPUID>();
for (int i = 0; i < 64; i++) {
try {
threads.Add(new CPUID(i));
} catch (ArgumentOutOfRangeException) { }
}
SortedDictionary<uint, List<CPUID>> processors =
new SortedDictionary<uint, List<CPUID>>();
foreach (CPUID thread in threads) {
List<CPUID> list;
processors.TryGetValue(thread.ProcessorId, out list);
if (list == null) {
list = new List<CPUID>();
processors.Add(thread.ProcessorId, list);
}
list.Add(thread);
}
CPUID[][] processorThreads = new CPUID[processors.Count][];
int index = 0;
foreach (List<CPUID> list in processors.Values) {
processorThreads[index] = list.ToArray();
index++;
}
return processorThreads;
}
public IntelCPU(int processorIndex, CPUID[][] cpuid, ISettings settings)
: base(processorIndex, cpuid, settings)
{
// set tjMax
float[] tjMax;
switch (family)
{
case 0x06:
{
switch (model)
{
case 0x0F: // Intel Core 2 (65nm)
microarchitecture = Microarchitecture.Core;
switch (stepping)
{
case 0x06: // B2
switch (coreCount)
{
case 2:
tjMax = Floats(80 + 10); break;
case 4:
tjMax = Floats(90 + 10); break;
default:
tjMax = Floats(85 + 10); break;
}
tjMax = Floats(80 + 10); break;
case 0x0B: // G0
tjMax = Floats(90 + 10); break;
case 0x0D: // M0
tjMax = Floats(85 + 10); break;
default:
tjMax = Floats(85 + 10); break;
}
break;
case 0x17: // Intel Core 2 (45nm)
microarchitecture = Microarchitecture.Core;
tjMax = Floats(100); break;
case 0x1C: // Intel Atom (45nm)
microarchitecture = Microarchitecture.Atom;
switch (stepping)
{
case 0x02: // C0
tjMax = Floats(90); break;
case 0x0A: // A0, B0
tjMax = Floats(100); break;
default:
tjMax = Floats(90); break;
}
break;
case 0x1A: // Intel Core i7 LGA1366 (45nm)
case 0x1E: // Intel Core i5, i7 LGA1156 (45nm)
case 0x1F: // Intel Core i5, i7
case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm)
case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core
case 0x2E: // Intel Xeon Processor 7500 series (45nm)
case 0x2F: // Intel Xeon Processor (32nm)
microarchitecture = Microarchitecture.Nehalem;
tjMax = GetTjMaxFromMSR();
break;
case 0x2A: // Intel Core i5, i7 2xxx LGA1155 (32nm)
case 0x2D: // Next Generation Intel Xeon, i7 3xxx LGA2011 (32nm)
microarchitecture = Microarchitecture.SandyBridge;
tjMax = GetTjMaxFromMSR();
break;
case 0x3A: // Intel Core i5, i7 3xxx LGA1155 (22nm)
case 0x3E: // Intel Core i7 4xxx LGA2011 (22nm)
microarchitecture = Microarchitecture.IvyBridge;
tjMax = GetTjMaxFromMSR();
break;
case 0x3C: // Intel Core i5, i7 4xxx LGA1150 (22nm)
case 0x3F: // Intel Xeon E5-2600/1600 v3, Core i7-59xx
// LGA2011-v3, Haswell-E (22nm)
case 0x45: // Intel Core i5, i7 4xxxU (22nm)
case 0x46:
microarchitecture = Microarchitecture.Haswell;
tjMax = GetTjMaxFromMSR();
break;
case 0x3D: // Intel Core M-5xxx (14nm)
microarchitecture = Microarchitecture.Broadwell;
tjMax = GetTjMaxFromMSR();
break;
case 0x36: // Intel Atom S1xxx, D2xxx, N2xxx (32nm)
microarchitecture = Microarchitecture.Atom;
tjMax = GetTjMaxFromMSR();
break;
case 0x37: // Intel Atom E3xxx, Z3xxx (22nm)
case 0x4A:
case 0x4D: // Intel Atom C2xxx (22nm)
case 0x5A:
case 0x5D:
microarchitecture = Microarchitecture.Silvermont;
tjMax = GetTjMaxFromMSR();
break;
default:
microarchitecture = Microarchitecture.Unknown;
tjMax = Floats(100);
break;
}
}
break;
case 0x0F:
{
switch (model)
{
case 0x00: // Pentium 4 (180nm)
case 0x01: // Pentium 4 (130nm)
case 0x02: // Pentium 4 (130nm)
case 0x03: // Pentium 4, Celeron D (90nm)
case 0x04: // Pentium 4, Pentium D, Celeron D (90nm)
case 0x06: // Pentium 4, Pentium D, Celeron D (65nm)
microarchitecture = Microarchitecture.NetBurst;
tjMax = Floats(100);
break;
default:
microarchitecture = Microarchitecture.Unknown;
tjMax = Floats(100);
break;
}
}
break;
default:
microarchitecture = Microarchitecture.Unknown;
tjMax = Floats(100);
break;
}
// set timeStampCounterMultiplier
switch (microarchitecture)
{
case Microarchitecture.NetBurst:
case Microarchitecture.Atom:
case Microarchitecture.Core:
{
uint eax, edx;
if (Ring0.Rdmsr(IA32_PERF_STATUS, out eax, out edx))
{
timeStampCounterMultiplier =
((edx >> 8) & 0x1f) + 0.5 * ((edx >> 14) & 1);
}
}
break;
case Microarchitecture.Nehalem:
case Microarchitecture.SandyBridge:
case Microarchitecture.IvyBridge:
case Microarchitecture.Haswell:
case Microarchitecture.Broadwell:
case Microarchitecture.Silvermont:
{
uint eax, edx;
if (Ring0.Rdmsr(MSR_PLATFORM_INFO, out eax, out edx))
{
timeStampCounterMultiplier = (eax >> 8) & 0xff;
}
}
break;
default:
timeStampCounterMultiplier = 0;
break;
}
// check if processor supports a digital thermal sensor at core level
if (cpuid[0][0].Data.GetLength(0) > 6 &&
(cpuid[0][0].Data[6, 0] & 1) != 0 &&
microarchitecture != Microarchitecture.Unknown)
{
coreTemperatures = new Sensor[coreCount];
for (int i = 0; i < coreTemperatures.Length; i++)
{
coreTemperatures[i] = new Sensor(CoreString(i), i,
SensorType.Temperature, this, new[] {
new ParameterDescription(
"TjMax [°C]", "TjMax temperature of the core sensor.\n" +
"Temperature = TjMax - TSlope * Value.", tjMax[i]),
new ParameterDescription("TSlope [°C]",
"Temperature slope of the digital thermal sensor.\n" +
"Temperature = TjMax - TSlope * Value.", 1)}, settings);
ActivateSensor(coreTemperatures[i]);
}
}
else
{
coreTemperatures = new Sensor[0];
}
// check if processor supports a digital thermal sensor at package level
if (cpuid[0][0].Data.GetLength(0) > 6 &&
(cpuid[0][0].Data[6, 0] & 0x40) != 0 &&
microarchitecture != Microarchitecture.Unknown)
{
packageTemperature = new Sensor("CPU Package",
coreTemperatures.Length, SensorType.Temperature, this, new[] {
new ParameterDescription(
"TjMax [°C]", "TjMax temperature of the package sensor.\n" +
"Temperature = TjMax - TSlope * Value.", tjMax[0]),
new ParameterDescription("TSlope [°C]",
"Temperature slope of the digital thermal sensor.\n" +
"Temperature = TjMax - TSlope * Value.", 1)}, settings);
ActivateSensor(packageTemperature);
}
busClock = new Sensor("Bus Speed", 0, SensorType.Clock, this, settings);
coreClocks = new Sensor[coreCount];
for (int i = 0; i < coreClocks.Length; i++)
{
coreClocks[i] =
new Sensor(CoreString(i), i + 1, SensorType.Clock, this, settings);
if (HasTimeStampCounter && microarchitecture != Microarchitecture.Unknown)
ActivateSensor(coreClocks[i]);
}
if (microarchitecture == Microarchitecture.SandyBridge ||
microarchitecture == Microarchitecture.IvyBridge ||
microarchitecture == Microarchitecture.Haswell ||
microarchitecture == Microarchitecture.Broadwell ||
microarchitecture == Microarchitecture.Silvermont)
{
powerSensors = new Sensor[energyStatusMSRs.Length];
lastEnergyTime = new DateTime[energyStatusMSRs.Length];
lastEnergyConsumed = new uint[energyStatusMSRs.Length];
uint eax, edx;
if (Ring0.Rdmsr(MSR_RAPL_POWER_UNIT, out eax, out edx))
switch (microarchitecture)
{
case Microarchitecture.Silvermont:
energyUnitMultiplier = 1.0e-6f * (1 << (int)((eax >> 8) & 0x1F));
break;
default:
energyUnitMultiplier = 1.0f / (1 << (int)((eax >> 8) & 0x1F));
break;
}
if (energyUnitMultiplier != 0)
{
for (int i = 0; i < energyStatusMSRs.Length; i++)
{
if (!Ring0.Rdmsr(energyStatusMSRs[i], out eax, out edx))
continue;
lastEnergyTime[i] = DateTime.UtcNow;
lastEnergyConsumed[i] = eax;
powerSensors[i] = new Sensor(powerSensorLabels[i], i,
SensorType.Power, this, settings);
ActivateSensor(powerSensors[i]);
}
}
}
Update();
}
public AMD10CPU(int processorIndex, CPUID[][] cpuid, ISettings settings)
: base(processorIndex, cpuid, settings)
{
// AMD family 1Xh processors support only one temperature sensor
coreTemperature = new Sensor(
"Core" + (coreCount > 1 ? " #1 - #" + coreCount : ""), 0,
SensorType.Temperature, this, new [] {
new ParameterDescription("Offset [°C]", "Temperature offset.", 0)
}, settings);
switch (family) {
case 0x10: miscellaneousControlDeviceId =
FAMILY_10H_MISCELLANEOUS_CONTROL_DEVICE_ID; break;
case 0x11: miscellaneousControlDeviceId =
FAMILY_11H_MISCELLANEOUS_CONTROL_DEVICE_ID; break;
case 0x12: miscellaneousControlDeviceId =
FAMILY_12H_MISCELLANEOUS_CONTROL_DEVICE_ID; break;
case 0x14: miscellaneousControlDeviceId =
FAMILY_14H_MISCELLANEOUS_CONTROL_DEVICE_ID; break;
case 0x15:
switch (model & 0xF0) {
case 0x00: miscellaneousControlDeviceId =
FAMILY_15H_MODEL_00_MISC_CONTROL_DEVICE_ID; break;
case 0x10: miscellaneousControlDeviceId =
FAMILY_15H_MODEL_10_MISC_CONTROL_DEVICE_ID; break;
default: miscellaneousControlDeviceId = 0; break;
} break;
case 0x16:
switch (model & 0xF0) {
case 0x00: miscellaneousControlDeviceId =
FAMILY_16H_MODEL_00_MISC_CONTROL_DEVICE_ID; break;
default: miscellaneousControlDeviceId = 0; break;
} break;
default: miscellaneousControlDeviceId = 0; break;
}
// get the pci address for the Miscellaneous Control registers
miscellaneousControlAddress = GetPciAddress(
MISCELLANEOUS_CONTROL_FUNCTION, miscellaneousControlDeviceId);
busClock = new Sensor("Bus Speed", 0, SensorType.Clock, this, settings);
coreClocks = new Sensor[coreCount];
for (int i = 0; i < coreClocks.Length; i++) {
coreClocks[i] = new Sensor(CoreString(i), i + 1, SensorType.Clock,
this, settings);
if (HasTimeStampCounter)
ActivateSensor(coreClocks[i]);
}
corePerformanceBoostSupport = (cpuid[0][0].ExtData[7, 3] & (1 << 9)) > 0;
// set affinity to the first thread for all frequency estimations
ulong mask = ThreadAffinity.Set(1UL << cpuid[0][0].Thread);
// disable core performance boost
uint hwcrEax, hwcrEdx;
Ring0.Rdmsr(HWCR, out hwcrEax, out hwcrEdx);
if (corePerformanceBoostSupport)
Ring0.Wrmsr(HWCR, hwcrEax | (1 << 25), hwcrEdx);
uint ctlEax, ctlEdx;
Ring0.Rdmsr(PERF_CTL_0, out ctlEax, out ctlEdx);
uint ctrEax, ctrEdx;
Ring0.Rdmsr(PERF_CTR_0, out ctrEax, out ctrEdx);
timeStampCounterMultiplier = estimateTimeStampCounterMultiplier();
// restore the performance counter registers
Ring0.Wrmsr(PERF_CTL_0, ctlEax, ctlEdx);
Ring0.Wrmsr(PERF_CTR_0, ctrEax, ctrEdx);
// restore core performance boost
if (corePerformanceBoostSupport)
Ring0.Wrmsr(HWCR, hwcrEax, hwcrEdx);
// restore the thread affinity.
ThreadAffinity.Set(mask);
// the file reader for lm-sensors support on Linux
temperatureStream = null;
int p = (int)Environment.OSVersion.Platform;
if ((p == 4) || (p == 128)) {
string[] devicePaths = Directory.GetDirectories("/sys/class/hwmon/");
foreach (string path in devicePaths) {
string name = null;
try {
using (StreamReader reader = new StreamReader(path + "/device/name"))
name = reader.ReadLine();
} catch (IOException) { }
switch (name) {
case "k10temp":
temperatureStream = new FileStream(path + "/device/temp1_input",
FileMode.Open, FileAccess.Read, FileShare.ReadWrite);
break;
}
}
}
Update();
}
public GenericCPU(int processorIndex, CPUID[][] cpuid, ISettings settings)
: base(cpuid[0][0].Name, CreateIdentifier(cpuid[0][0].Vendor,
processorIndex), settings)
{
this.cpuid = cpuid;
this.vendor = cpuid[0][0].Vendor;
this.family = cpuid[0][0].Family;
this.model = cpuid[0][0].Model;
this.stepping = cpuid[0][0].Stepping;
this.processorIndex = processorIndex;
this.coreCount = cpuid.Length;
// check if processor has MSRs
if (cpuid[0][0].Data.GetLength(0) > 1
&& (cpuid[0][0].Data[1, 3] & 0x20) != 0)
hasModelSpecificRegisters = true;
else
hasModelSpecificRegisters = false;
// check if processor has a TSC
if (cpuid[0][0].Data.GetLength(0) > 1
&& (cpuid[0][0].Data[1, 3] & 0x10) != 0)
hasTimeStampCounter = true;
else
hasTimeStampCounter = false;
// check if processor supports an invariant TSC
if (cpuid[0][0].ExtData.GetLength(0) > 7
&& (cpuid[0][0].ExtData[7, 3] & 0x100) != 0)
isInvariantTimeStampCounter = true;
else
isInvariantTimeStampCounter = false;
if (coreCount > 1)
totalLoad = new Sensor("CPU Total", 0, SensorType.Load, this, settings);
else
totalLoad = null;
coreLoads = new Sensor[coreCount];
for (int i = 0; i < coreLoads.Length; i++)
coreLoads[i] = new Sensor(CoreString(i), i + 1,
SensorType.Load, this, settings);
cpuLoad = new CPULoad(cpuid);
if (cpuLoad.IsAvailable)
{
foreach (Sensor sensor in coreLoads)
ActivateSensor(sensor);
if (totalLoad != null)
ActivateSensor(totalLoad);
}
if (hasTimeStampCounter)
{
ulong mask = ThreadAffinity.Set(1UL << cpuid[0][0].Thread);
EstimateTimeStampCounterFrequency(
out estimatedTimeStampCounterFrequency,
out estimatedTimeStampCounterFrequencyError);
ThreadAffinity.Set(mask);
}
else
{
estimatedTimeStampCounterFrequency = 0;
}
timeStampCounterFrequency = estimatedTimeStampCounterFrequency;
}
