public IxgbeDevice(string pciAddr, int rxQueues, int txQueues)
: base(pciAddr, rxQueues, txQueues)
{
if (txQueues < 0 || txQueues > MaxQueues)
{
throw new ArgumentException(String.Format("Cannot configure {0} tx queues - limit is {1}",
txQueues, MaxQueues));
}
if (rxQueues < 0 || rxQueues > MaxQueues)
{
throw new ArgumentException(String.Format("Cannot configure {0} rx queues - limit is {1}",
rxQueues, MaxQueues));
}
DriverName = "ixy-ixgbe";
RxQueues = new IxgbeRxQueue[rxQueues];
TxQueues = new IxgbeTxQueue[txQueues];
PciController.RemoveDriver(pciAddr);
PciController.EnableDma(pciAddr);
try
{
//View accessor for mmapped file is automatically created
PciMemMap = PciController.MapResource(pciAddr);
}
catch (Exception e)
{
Log.Error("FATAL: Could not map memory for device {0} - {1}", pciAddr, e.Message);
Environment.Exit(1);
}
ResetAndInit();
}
//Section 4.6.8
private void InitTx()
{
//CRC offload and small packet padding
SetFlags(IxgbeDefs.HLREG0, IxgbeDefs.HLREG0_TXCRCEN | IxgbeDefs.HLREG0_TXPADEN);
//Set default buffer size allocations (section 4.6.11.3.4)
SetReg(IxgbeDefs.TXPBSIZE(0), IxgbeDefs.TXPBSIZE_40KB);
for (uint i = 1; i < 8; i++)
{
SetReg(IxgbeDefs.TXPBSIZE(i), 0);
}
//Required when not using DCB/VTd
SetReg(IxgbeDefs.DTXMXSZRQ, 0xFFFF);
ClearFlags(IxgbeDefs.RTTDCS, IxgbeDefs.RTTDCS_ARBDIS);
//Per queue config for all queues
for (uint i = 0; i < TxQueues.Length; i++)
{
Log.Notice("Initializing TX queue {0}", i);
//Section 7.1.9 - Setup descriptor ring
uint ringSizeBytes = NumTxQueueEntries * TxDescriptorSize;
var dmaMem = MemoryHelper.AllocateDmaC(ringSizeBytes, true);
//TODO : The C version sets the allocated memory to -1 here
SetReg(IxgbeDefs.TDBAL(i), (uint)(dmaMem.PhysicalAddress & 0xFFFFFFFFL));
SetReg(IxgbeDefs.TDBAH(i), (uint)(dmaMem.PhysicalAddress >> 32));
SetReg(IxgbeDefs.TDLEN(i), (uint)ringSizeBytes);
Log.Notice("TX ring {0} physical addr: {1}", i, dmaMem.PhysicalAddress);
Log.Notice("TX ring {0} virtual addr: {1}", i, dmaMem.VirtualAddress);
//Descriptor writeback magic values, important to get good performance and low PCIe overhead
//See sec. 7.2.3.4.1 and 7.2.3.5
uint txdctl = GetReg(IxgbeDefs.TXDCTL(i));
//Seems like overflow is irrelevant here
unchecked
{
//Clear bits
txdctl &= (uint)(~(0x3F | (0x3F << 8) | (0x3F << 16)));
//From DPDK
txdctl |= (36 | (8 << 8) | (4 << 16));
}
SetReg(IxgbeDefs.TXDCTL(i), txdctl);
var queue = new IxgbeTxQueue(NumTxQueueEntries);
queue.Index = 0;
queue.DescriptorsAddr = dmaMem.VirtualAddress;
TxQueues[i] = queue;
}
//Enable DMA
SetReg(IxgbeDefs.DMATXCTL, IxgbeDefs.DMATXCTL_TE);
}
