private RegisterCollection AddBank(RegisterCollection.TType aType, RegisterCollection aLinkedWith, params TArmRegisterType[] aExtraRegs)
{
RegisterCollection bank = new RegisterCollection(CrashDebugger, aType, null, aLinkedWith);
iBanks.Add(aType, bank);
// Create bank specific registers
string bankName = RegisterCollection.BankName(aType);
if (bankName != string.Empty)
{
bankName = "_" + bankName;
}
bank.Add("R13" + bankName, 0);
bank.Add("R14" + bankName, 0);
bank.Add("SPSR" + bankName, 0);
// Create custom registers
foreach (TArmRegisterType custom in aExtraRegs)
{
string name = ArmRegister.GetTypeName(custom) + bankName;
bank.Add(name, 0);
}
return(bank);
}
internal RegisterCollection(RegisterCollection aCopy, TType aType, DProcess aProcess)
: this(aCopy.CrashDebugger, aType, aProcess, null)
{
foreach (RegisterEntry entry in aCopy)
{
Add(entry.OriginalName, entry.Value);
}
}
public RegisterEntry this[RegisterCollection.TType aBank, TArmRegisterType aType]
{
get
{
RegisterCollection bank = this[aBank];
return(bank[aType]);
}
}
public RegisterEntry this[RegisterCollection.TType aBank, string aName]
{
get
{
RegisterCollection bank = this[aBank];
return(bank[aName]);
}
}
public RegisterCollection this[RegisterCollection.TType aBank]
{
get
{
RegisterCollection ret = iBanks[aBank];
return(ret);
}
}
internal RegisterCollection(CrashDebuggerInfo aCrashDebugger, TType aType, DProcess aProcess, RegisterCollection aLinkedWith)
: base(aCrashDebugger)
{
iType = aType;
iProcess = aProcess;
iEntries = new ArmRegisterCollection();
iEntries.BackingStore = this as IARCBackingStore;
iLinkedWith = aLinkedWith;
}
public void Clear()
{
iBanks.Clear();
// General regs don't share a bank - they're just a dumping
// ground for CPU specific entries.
AddBank(RegisterCollection.TType.ETypeGeneral);
// The rest use banking. CPSR goes in the common bank.
RegisterCollection common = new RegisterCollection(CrashDebugger, RegisterCollection.TType.ETypeCommonBank);
iBanks.Add(RegisterCollection.TType.ETypeCommonBank, common);
common.AddMany(TArmRegisterType.EArmReg_CPSR,
TArmRegisterType.EArmReg_00,
TArmRegisterType.EArmReg_01,
TArmRegisterType.EArmReg_02,
TArmRegisterType.EArmReg_03,
TArmRegisterType.EArmReg_04,
TArmRegisterType.EArmReg_05,
TArmRegisterType.EArmReg_06,
TArmRegisterType.EArmReg_07);
// These are all fairly normal. They have their own SP, LR and SPSR
// The others are common.
AddBank(RegisterCollection.TType.ETypeUser, common);
AddBank(RegisterCollection.TType.ETypeAbort, common);
AddBank(RegisterCollection.TType.ETypeInterrupt, common);
AddBank(RegisterCollection.TType.ETypeSupervisor, common);
AddBank(RegisterCollection.TType.ETypeSystem, common);
AddBank(RegisterCollection.TType.ETypeUndefined, common);
// FIQ is special - it has shadows of R8->12
AddBank(RegisterCollection.TType.ETypeFastInterrupt, common,
TArmRegisterType.EArmReg_08,
TArmRegisterType.EArmReg_09,
TArmRegisterType.EArmReg_10,
TArmRegisterType.EArmReg_11,
TArmRegisterType.EArmReg_12
);
}
internal RegisterEntryCPSR(RegisterCollection aParent, uint aValue)
: base(aParent, ArmRegister.GetTypeName(TArmRegisterType.EArmReg_CPSR), aValue)
{
}
internal RegisterEntry(RegisterCollection aParent, string aName, uint aValue)
: base(aName, aValue)
{
iParent = aParent;
}
internal RegisterEntry(RegisterCollection aParent, TArmRegisterType aType)
: base(aType)
{
iParent = aParent;
}
private RegisterCollection AddBank(RegisterCollection.TType aType, RegisterCollection aLinkedWith)
{
TArmRegisterType[] empty = new TArmRegisterType[] { };
return(AddBank(aType, aLinkedWith, empty));
}
