public override void Analyze(Analysis Mna)
{
Diode.Analyze(Mna, Gate, Source, IS, n);
Diode.Analyze(Mna, Gate, Drain, IS, n);
// The drain and source terminals are reversible in the JFET model, this
// formulation is simpler than explicitly identifying normal/inverted mode.
Expression Vgds = Gate.V - Call.Min(Source.V, Drain.V);
Expression Vds = Drain.V - Source.V;
Expression AbsVds = Call.Abs(Vds);
//Vgds = Mna.AddUnknownEqualTo(Name + "gds", Vgds);
Expression Vgds_t0 = Vgds - Vt0;
Expression id = Call.Sign(Vds) * (Vgds >= Vt0) * Beta * (1 + Lambda * AbsVds) *
Call.If(AbsVds < Vgds_t0,
// Linear region.
AbsVds * (2 * Vgds_t0 - 1),
// Saturation region.
Vgds_t0 ^ 2);
id = Mna.AddUnknownEqualTo("i" + Name + "d", id);
CurrentSource.Analyze(Mna, Drain, Source, id);
}
public override void Analyze(Analysis Mna)
{
// Implement Voltage gain.
Node pp1 = new Node()
{
Name = "pp1"
};
Node np1 = new Node()
{
Name = "np1"
};
Mna.PushContext(Name, pp1, np1);
// The input terminals are connected by a resistor Rin.
Resistor.Analyze(Mna, Negative, Positive, Rin);
Expression VRin = Negative.V - Positive.V;
Expression Rp1 = 1000;
CurrentSource.Analyze(Mna, pp1, np1, VRin * Aol / Rp1);
Resistor.Analyze(Mna, pp1, np1, Rp1);
Capacitor.Analyze(Mna, pp1, np1, 1 / (2 * Math.PI * Rp1 * GBP / Aol));
Ground.Analyze(Mna, np1);
// Implement voltage limiter.
if (vcc.IsConnected && vee.IsConnected)
{
Node ncc = new Node()
{
Name = "ncc"
};
Node nee = new Node()
{
Name = "nee"
};
Mna.DeclNodes(ncc, nee);
VoltageSource.Analyze(Mna, vcc, ncc, 2);
Diode.Analyze(Mna, pp1, ncc, 8e-16, 1, VT);
VoltageSource.Analyze(Mna, vee, nee, -2);
Diode.Analyze(Mna, nee, pp1, 8e-16, 1, VT);
}
// Output current is buffered.
Mna.AddTerminal(Out, (pp1.V - Out.V) / Rout);
Mna.PopContext();
}
