private LibraryElement GetLibraryElement()
{
LibraryElement el = new LibraryElement();
el.Name = Name;
el.PrimitiveName = BELType;
el.VHDLGenericMap = "generic map ( INIT => X\"ABCDABCDABCDABCD\" )";
el.Containter = new XDLModule();
el.VivadoConnectionPrimitive = true;
// add outpin
XDLPort outPort = new XDLPort();
outPort.Direction = FPGATypes.PortDirection.Out;
outPort.ExternalName = "O";
outPort.InstanceName = "unknown";
outPort.SlicePort = "unknown";
el.Containter.Add(outPort);
// add inpins
for (int i = 0; i < LUT_SIZE; i++)
{
AddXDLPort(el, $"I{i}", FPGATypes.PortDirection.In);
}
return(el);
}
private void AddXDLPort(LibraryElement el, string portName, FPGATypes.PortDirection dir)
{
XDLPort p = new XDLPort();
p.Direction = dir;
p.ExternalName = portName;
p.InstanceName = "unknown";
p.SlicePort = "unknown";
p.ConstantValuePort = false;
el.Containter.Add(p);
}
private void AddXDLPort(LibraryElement el, string prefix, int index, FPGATypes.PortDirection dir, bool makeInputsConstant)
{
XDLPort p = new XDLPort();
p.Direction = dir;
p.ExternalName = prefix + index;
p.InstanceName = "unknown";
p.SlicePort = "unknown";
p.ConstantValuePort = makeInputsConstant;
el.Containter.Add(p);
}
private LibraryElement GetFF(string belName, bool makeInputsConstant, string inputPortPrefix, string outputPort)
{
LibraryElement el = new LibraryElement();
el.SliceNumber = SliceNumber;
el.Name = belName;
el.PrimitiveName = BELType;
el.BEL = belName;
el.LoadCommand = ToString();
el.Containter = new NetlistContainer();
el.VHDLGenericMap = "generic map ( INIT => '0' )";
el.Containter = new XDLModule();
el.VivadoConnectionPrimitive = true;
// Q output
XDLPort q = new XDLPort();
q.Direction = FPGATypes.PortDirection.Out;
q.ExternalName = "Q";
q.InstanceName = "unknown";
q.SlicePort = "unknown";
el.Containter.Add(q);
List <string> inputs = new List <string>();
inputs.Add("D");
inputs.Add("C");
inputs.Add("CE");
inputs.Add("R");
foreach (string i in inputs)
{
XDLPort p = new XDLPort();
p.Direction = FPGATypes.PortDirection.In;
p.ExternalName = i;
p.InstanceName = "unknown";
p.SlicePort = "unknown";
p.ConstantValuePort = false;
el.Containter.Add(p);
}
;
Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
foreach (string stopOverPortName in StopOverPorts)
{
el.AddPortToBlock(interconnect, new Port(stopOverPortName));
}
return(el);
}
public static bool HasMapping(XDLPort port, Dictionary <string, string> portMapping, out string portMappingKey)
{
portMappingKey = "";
foreach (string key in portMapping.Keys)
{
//if (port.ExternalName.Equals(key))
if (Regex.IsMatch(port.ExternalName, key))
{
portMappingKey = key;
return(true);
}
}
return(false);
}
private LibraryElement GetLUT(string belName, bool makeInputsConstant, string inputPortPrefix, string outputPort, string initValue)
{
int lutSize = 6;
LibraryElement el = new LibraryElement();
el.SliceNumber = SliceNumber;
el.Name = belName;
el.PrimitiveName = BELType;
el.BEL = belName;
el.LoadCommand = ToString();
el.Containter = new NetlistContainer();
el.VHDLGenericMap = "generic map ( INIT => X\"" + initValue + "\" )";
el.Containter = new XDLModule();
el.VivadoConnectionPrimitive = true;
// one output per LUT
XDLPort outPort = new XDLPort();
outPort.Direction = FPGATypes.PortDirection.Out;
outPort.ExternalName = "O";
outPort.InstanceName = "unknown";
outPort.SlicePort = "unknown";
el.Containter.Add(outPort);
// six inputs I=..I5
for (int i = 0; i < lutSize; i++)
{
AddXDLPort(el, "I", i, FPGATypes.PortDirection.In, makeInputsConstant);
}
Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
List <string> lutPortNames = new List <string>();
// see LUTRouting tab
for (int i = 1; i <= lutSize; i++)
{
lutPortNames.Add(inputPortPrefix + i);
}
foreach (string stopOverPortName in StopOverPorts)
{
el.AddPortToBlock(interconnect, new Port(stopOverPortName));
}
return(el);
}
public override void Do()
{
Slice where = FPGA.FPGA.Instance.Current.Slices[this.SliceNumber];
m_addedPort = new XDLPort(this.PortName, new Port(this.PortString), where);
MacroManager.Instance.CurrentMacro.Add(this.m_addedPort);
}