private IEnumerable <string> GetCSVString(VHDLParserEntity entity, HDLEntitySignal signal, FPGA.FPGATypes.Direction direction) { int to = Math.Max(signal.MSB, signal.LSB); int from = Math.Min(signal.MSB, signal.LSB); for (int index = to; index >= from; index--) { // no nam string line = signal.SignalName + "(" + index + ")," + signal.SignalDirection + "," + direction + "," + entity.EntityName + "," + signal.MetaData.Column; yield return(line); } }
protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE); DesignParser parser = DesignParser.CreateDesignParser(XDLFile); XDLContainer container = new XDLContainer(); parser.ParseDesign(container, this); VHDLParser moduleParser = new VHDLParser(VHDLModule); VHDLParserEntity ent = moduleParser.GetEntity(0); Dictionary <int, List <Signal> > east = new Dictionary <int, List <Signal> >(); Dictionary <int, List <Signal> > west = new Dictionary <int, List <Signal> >(); double xCenter, yCenter; TileSelectionManager.Instance.GetCenterOfSelection(t => TileSelectionManager.Instance.IsSelected(t.TileKey), out xCenter, out yCenter); foreach (HDLEntitySignal signal in ent.InterfaceSignals) { foreach (XDLNet net in container.Nets.Where(n => n.Name.StartsWith(signal.SignalName) && ((XDLNet)n).HasIndex()).OrderBy(n => ((XDLNet)n).GetIndex())) { Tile fromTile; Tile toTile; GetSourceAndSink(container, net, out fromTile, out toTile); GetSourceAndSink(container, net, out fromTile, out toTile); Tile innerTile = null; Tile outerTile = null; string signalMode = ""; if (!TileSelectionManager.Instance.IsSelected(fromTile.TileKey) && TileSelectionManager.Instance.IsSelected(toTile.TileKey)) { innerTile = toTile; outerTile = fromTile; signalMode = "in"; } else if (TileSelectionManager.Instance.IsSelected(fromTile.TileKey) && !TileSelectionManager.Instance.IsSelected(toTile.TileKey)) { outerTile = toTile; innerTile = fromTile; signalMode = "out"; } else { throw new ArgumentException("Expecting an instance inside the current selection"); } FPGATypes.InterfaceDirection dir = outerTile.TileKey.X < (int)xCenter ? FPGATypes.InterfaceDirection.East : FPGATypes.InterfaceDirection.West; Dictionary <int, List <Signal> > signalCollection = dir.Equals(FPGATypes.InterfaceDirection.East) ? east : west; if (!signalCollection.ContainsKey(innerTile.TileKey.Y)) { signalCollection.Add(innerTile.TileKey.Y, new List <Signal>()); } Signal s = new Signal(); s.Column = -1; s.SignalDirection = dir; s.SignalMode = signalMode; s.SignalName = net.Name; signalCollection[innerTile.TileKey.Y].Add(s); // weiter: vor verlaesst das gummiband die partielle flaeche? // vektoren nach osten oder westen? } } bool interleaveEast = east.Any(t => t.Value.Count > 4); bool interleaveWest = west.Any(t => t.Value.Count > 4); Dictionary <FPGA.FPGATypes.Direction, Dictionary <int, List <Signal> > > interfaces = new Dictionary <FPGATypes.Direction, Dictionary <int, List <Signal> > >(); interfaces.Add(FPGATypes.Direction.East, new Dictionary <int, List <Signal> >()); interfaces[FPGATypes.Direction.East][0] = new List <Signal>(); interfaces[FPGATypes.Direction.East][1] = new List <Signal>(); interfaces.Add(FPGATypes.Direction.West, new Dictionary <int, List <Signal> >()); interfaces[FPGATypes.Direction.West][0] = new List <Signal>(); interfaces[FPGATypes.Direction.West][1] = new List <Signal>(); if (interleaveEast) { int columnIndex = 0; foreach (KeyValuePair <int, List <Signal> > tupel in east) { foreach (Signal s in tupel.Value) { Signal copy = new Signal(s.SignalName, s.SignalMode, s.SignalDirection, "", columnIndex); interfaces[FPGATypes.Direction.East][columnIndex].Add(copy); columnIndex++; columnIndex %= 2; } } } //ent.InterfaceSignals }