TCLObjectList FileName(TCLObjectList source)
{
if (source == null)
{
return(null);
}
return(new TCLObjectList(source.Objects.Select(FileName).ToList()));
}
/// <summary>
/// <para>
/// Remove Pblock<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: delete_pblocks [-hier] [-quiet] [-verbose] <pblocks>...
/// <br/>
/// <para>
/// Deletes the specified Pblocks from the design. Pblocks are created using the create_pblock<br/>
/// command.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example deletes the specified Pblock as well as any Pblocks nested inside:<br/>
/// delete_pblocks -hier cpuEngine<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 463<br/>
/// </para>
/// </summary>
/// <param name="pblocks">(Required) Pblocks to delete</param>
/// <param name="hier">(Optional) Also delete all the children of Pblock</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL delete_pblocks(TCLObjectList pblocks, bool?hier = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: delete_pblocks [-hier] [-quiet] [-verbose] <pblocks>...
_tcl.Entry(_builder.delete_pblocks(pblocks, hier, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Set user columns on one or more package pins<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: set_package_pin_val [-quiet] [-verbose] <column> <value> <package_pins>...
/// <br/>
/// <para>
/// Create user-defined package pin attributes and assign values to specific pins on the package.<br/>
/// User-defined pin attributes can be defined in a CSV file and imported into an I/O Pin Planning<br/>
/// project using read_csv, or can be edited in the project using this command.<br/>
/// Note: Use the set_property command to set tool-defined properties of a package pin.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example creates a new user-defined column in the Package Pins view, and assigns<br/>
/// the value true to the specified pin:<br/>
/// set_package_pin_val -column track1 -value true -package_pins AK27<br/>
/// The following example creates a user-defined column called Test, then assigns the value RED to<br/>
/// all "AK" package pins, then changes the value to GREEN for the three specified pins:<br/>
/// set_package_pin_val -column Test -value RED \<br/>
/// -package_pins [get_package_pins AK*]<br/>
/// set_package_pin_val -column Test -value GREEN \<br/>
/// -package_pins {AK1 AK2 AK3}<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1670<br/>
/// </para>
/// </summary>
/// <param name="column">(Required) User column name</param>
/// <param name="value">(Required) Value to set</param>
/// <param name="package_pins">(Required) Package pin names</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL set_package_pin_val(TCLObject column, TCLObject value, TCLObjectList package_pins, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: set_package_pin_val [-quiet] [-verbose] <column> <value> <package_pins>...
_tcl.Entry(_builder.set_package_pin_val(column, value, package_pins, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Remove the given list of top ports from the netlist.<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: remove_port [-quiet] [-verbose] <ports>...
/// <br/>
/// <para>
/// Removes the specified ports or buses.<br/>
/// To remove a bus port, you must specify the primary port name, and not specify a bus index. This<br/>
/// ensures that the entire bus port is removed, and not just a portion of the bits associated with the<br/>
/// bus. You can resize a bus port, eliminating bits, using the resize_port_bus command.<br/>
/// The remove_port command will remove ports that have been added with the create_port<br/>
/// command, but cannot delete ports that are defined in the RTL or netlist design.<br/>
/// Netlist editing changes the in-memory view of the netlist in the current design. It does not<br/>
/// change the files in the source fileset, or change the persistent design on the disk. Changes made<br/>
/// to the netlist may be saved to a design checkpoint using the write_checkpoint command, or<br/>
/// may be exported to a netlist file such as Verilog, VHDL, or EDIF, using the appropriate write_*<br/>
/// command.<br/>
/// Note: Netlist editing is not allowed on the elaborated RTL design.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example deletes the specified port:<br/>
/// remove_port PORT0<br/>
/// The following example deletes the two specified ports of a bus:<br/>
/// remove_port BUS[1] BUS[2]<br/>
/// The following example deletes both the N and P sides of a differential pair port:<br/>
/// remove_port D_BUS_P[0]<br/>
/// Note: Deleting either the N or the P side of a differential pair will also delete the other side of the pair.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1272<br/>
/// </para>
/// </summary>
/// <param name="ports">(Required) Ports and/or bus ports to remove</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL remove_port(TCLObjectList ports, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: remove_port [-quiet] [-verbose] <ports>...
_tcl.Entry(_builder.remove_port(ports, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Delete I/O port interfaces from the project<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: delete_interface [-all] [-quiet] [-verbose] <interfaces>...
/// <br/>
/// <para>
/// Deletes an existing interface and optionally deletes all of the associated ports and buses using<br/>
/// the interface.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example deletes the specified interface and all of its associated ports and buses:<br/>
/// delete_interface USB0<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 455<br/>
/// </para>
/// </summary>
/// <param name="interfaces">(Required) I/O port interfaces to remove</param>
/// <param name="all">(Optional) Also remove all of the ports and buses belonging to the interface</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL delete_interface(TCLObjectList interfaces, bool?all = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: delete_interface [-all] [-quiet] [-verbose] <interfaces>...
_tcl.Entry(_builder.delete_interface(interfaces, all, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Reset switching activity on specified objects<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: reset_switching_activity [-default] [-type <args>] [-hier] [-all] [-no_deassert_resets] [-quiet] [-verbose] [<objects>...]
/// <br/>
/// <para>
/// Resets the attributes of the switching activity on specified nets, ports, pins, and cells in the<br/>
/// design.<br/>
/// The switching activity is defined using the set_switching_activity command. The current<br/>
/// switching activity defined for a specific port, pin, net, or cell can be found by using the<br/>
/// report_switching_activity command.<br/>
/// Note: The reset_switching_activity is used to reset switching activity for specified objects. Use<br/>
/// set_switching_activity -default_toggle_rate or -default_static_probability to<br/>
/// change or reset the default values for the current design.<br/>
/// This command operates silently and does not return direct feedback of its operation.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following example resets the signal_rate and static probability value on all output ports:<br/>
/// reset_switching_activity -default [all_outputs]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1518<br/>
/// </para>
/// </summary>
/// <param name="default">(Optional) Reset default static probability and default toggle rate</param>
/// <param name="type">
/// <para>
/// (Optional)<br/>
/// Specify nodes in a specific category. List of valid type values:<br/>
/// io_output, io_bidir_enable, register, lut_ram, lut, dsp,<br/>
/// bram_enable, bram_wr_enable, gt_txdata, gt_rxdata.<br/>
/// </para>
/// </param>
/// <param name="hier">
/// <para>
/// (Optional)<br/>
/// Hierarchically resets the switching activity on a hierarchical<br/>
/// cells provided as <objects>.<br/>
/// </para>
/// </param>
/// <param name="all">(Optional) Reset switching activity on all nets</param>
/// <param name="no_deassert_resets">
/// <para>
/// (Optional)<br/>
/// A switch to undo the deassertion of resets via command<br/>
/// set_switching_activity -deassert_resets<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="objects">(Optional) Objects to reset switching activity on</param>
public TTCL reset_switching_activity(bool? @default = null, TCLParameterList type = null, bool?hier = null, bool?all = null, bool?no_deassert_resets = null, bool?quiet = null, bool?verbose = null, TCLObjectList objects = null)
{
// TCL Syntax: reset_switching_activity [-default] [-type <args>] [-hier] [-all] [-no_deassert_resets] [-quiet] [-verbose] [<objects>...]
_tcl.Entry(_builder.reset_switching_activity(@default, type, hier, all, no_deassert_resets, quiet, verbose, objects));
return(_tcl);
}
/// <summary>
/// <para>
/// rename a port<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: rename_port -to <arg> [-quiet] [-verbose] <port>...
/// <br/>
/// <para>
/// Rename a single port in the current synthesized or implemented design.<br/>
/// TIP: You cannot rename individual bits of a bus port, but you can collectively rename the whole bus.<br/>
/// Netlist editing changes the in-memory view of the netlist in the current design. It does not<br/>
/// change the files in the source fileset, or change the persistent design on the disk. Changes made<br/>
/// to the netlist may be saved to a design checkpoint using the write_checkpoint command, or<br/>
/// may be exported to a netlist file such as Verilog, VHDL, or EDIF, using the appropriate write_*<br/>
/// command.<br/>
/// Note: Netlist editing is not allowed on the elaborated RTL design.<br/>
/// Changes to the names of cells, nets, pins, and ports, will also affect the design constraints defined<br/>
/// in the in-memory design. Constraints are automatically modified to target the new object name,<br/>
/// however these are not written back to the source XDC file. Saving the modified in-memory<br/>
/// design using write_checkpoint will save both the renamed objects and modified constraints.<br/>
/// This command returns nothing if successful, or an error if it fails.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following example renames the specified bus port:<br/>
/// rename_port -to wbInputData wbInDat<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1282<br/>
/// </para>
/// </summary>
/// <param name="to">(Required) New name</param>
/// <param name="port">(Required) Port to rename</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL rename_port(String to, TCLObjectList port, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: rename_port -to <arg> [-quiet] [-verbose] <port>...
_tcl.Entry(_builder.rename_port(to, port, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Remove nets from the current design<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: remove_net [-prune] [-quiet] [-verbose] <nets>...
/// <br/>
/// <para>
/// Remove the specified net from the netlist of an open Synthesized or Implemented Design.<br/>
/// Note: You cannot remove nets from library macros, also called macro-primitives.<br/>
/// To remove a bus, you must specify the primary bus name, and not specify a bus index. This<br/>
/// ensures that the entire bus is removed, and not just a portion of the bits associated with the bus.<br/>
/// You can resize a bus, eliminating bits of the bus, using the resize_net_bus command.<br/>
/// Netlist editing changes the in-memory view of the netlist in the current design. It does not<br/>
/// change the files in the source fileset, or change the persistent design on the disk. Changes made<br/>
/// to the netlist may be saved to a design checkpoint using the write_checkpoint command, or<br/>
/// may be exported to a netlist file such as Verilog, VHDL, or EDIF, using the appropriate write_*<br/>
/// command.<br/>
/// Note: Netlist editing is not allowed on the elaborated RTL design.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1268<br/>
/// </para>
/// </summary>
/// <param name="nets">(Required) List of nets to remove</param>
/// <param name="prune">
/// <para>
/// (Optional)<br/>
/// When performing net removal, remove pins and ports which<br/>
/// are left unconnected as a result of the remove_net<br/>
/// operation.<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL remove_net(TCLObjectList nets, bool?prune = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: remove_net [-prune] [-quiet] [-verbose] <nets>...
_tcl.Entry(_builder.remove_net(nets, prune, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Remove one or more custom command arguments<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: remove_gui_custom_command_args -command_name <arg> [-quiet] [-verbose] <names>...
/// <br/>
/// <para>
/// Remove one or more GUI custom command arguments of a particular GUI custom command.<br/>
/// You can use the get_gui_custom_commands to determine the list of defined custom<br/>
/// commands. You can use the get_gui_custom_command_args to determine the list of<br/>
/// defined GUI custom command arguments for a particular GUI custom command.<br/>
/// </para>
/// <br/>
/// <para>
/// Remove GUI custom command arguments with name 'arg1' and 'arg2' of a GUI custom command<br/>
/// with name 'cmd_1' :<br/>
/// remove_gui_custom_command_args -command_name cmd_1 {arg1 arg2}<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1252<br/>
/// </para>
/// </summary>
/// <param name="command_name">(Required) name of custom command whose arguments are being removed.</param>
/// <param name="names">(Required) name of one or more custom command arguments to remove.</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL remove_gui_custom_command_args(String command_name, TCLObjectList names, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: remove_gui_custom_command_args -command_name <arg> [-quiet] [-verbose] <names>...
_tcl.Entry(_builder.remove_gui_custom_command_args(command_name, names, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Get custom commands<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: get_gui_custom_commands [-regexp] [-nocase] [-quiet] [-verbose] [<patterns>...]
/// <br/>
/// <para>
/// Returns the list of GUI custom commands.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example returns a list of all the GUI custom commands which has names starting<br/>
/// with 'p':<br/>
/// get_gui_custom_commands p*<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 703<br/>
/// </para>
/// </summary>
/// <param name="regexp">(Optional) Patterns are full regular expressions</param>
/// <param name="nocase">(Optional) Perform case-insensitive matching (valid only when -regexp specified)</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="patterns">(Optional) Match the custom command names against patterns Default: *</param>
/// <returns>list of custom command names</returns>
public TTCL get_gui_custom_commands(bool?regexp = null, bool?nocase = null, bool?quiet = null, bool?verbose = null, TCLObjectList patterns = null)
{
// TCL Syntax: get_gui_custom_commands [-regexp] [-nocase] [-quiet] [-verbose] [<patterns>...]
_tcl.Entry(_builder.get_gui_custom_commands(regexp, nocase, quiet, verbose, patterns));
return(_tcl);
}
/// <summary>
/// <para>
/// Set property on object(s)<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: set_property [-dict <args>] [-quiet] [-verbose] <name> <value> <objects>...
/// <br/>
/// <para>
/// Assigns the defined property <name> and <value> to the specified <objects>.<br/>
/// This command can be used to define any property on an object in the design. Each object has a<br/>
/// set of predefined properties that have expected values, or a range of values. The set_property<br/>
/// command can be used to define the values for these properties. To determine the defined set of<br/>
/// properties on an object, use report_property, list_property, or<br/>
/// list_property_values.<br/>
/// You can also define custom properties for an object, by specifying a unique <name> and <value><br/>
/// pair for the object. If an object has custom properties, these will also be reported by the<br/>
/// report_property and list_property commands.<br/>
/// This command returns nothing if successful, and an error if it fails.<br/>
/// TIP: You can use the get_property command to validate any properties that have been set on an<br/>
/// object.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// Create a user-defined boolean property, TRUTH, for cell objects, and set the property on a cell:<br/>
/// create_property -type bool truth cell<br/>
/// set_property truth false [lindex [get_cells] 1]<br/>
/// Use the -dict option to specify multiple properties at one time on the current design:<br/>
/// set_property -dict "POST_CRC enable POST_CRC_ACTION correct_and_continue"<br/>
/// \<br/>
/// [current_design]<br/>
/// The following example sets the TOP property of the current fileset to define the top module of<br/>
/// the project:<br/>
/// set_property top fftTop [current_fileset]<br/>
/// set_property top_file {C:/Data/sources/fftTop.v} [current_fileset]<br/>
/// Note: Defining the top module requires the TOP property to be set to the desired hierarchical block in the<br/>
/// source fileset of the current project. In the preceding example TOP is the property name, fftTop is the<br/>
/// value, and current_fileset is the object. In addition, the TOP_FILE property should be defined to point to<br/>
/// the data source for the top module.<br/>
/// This example shows how to set a property value that includes the dash character, '-'. The dash<br/>
/// can cause the tool to interpret the value as a new command argument, rather than part of the<br/>
/// value being specified, and will cause an error as shown. In this case, you must use the explicit<br/>
/// form of the positional arguments in the set_property command:<br/>
/// set_property {XELAB.MORE_OPTIONS} {-pulse_e_style ondetect} \<br/>
/// [get_filesets sim_1]<br/>
/// ERROR: [Common 17-170] Unknown option '-pulse_e_style ondetect',<br/>
/// please type 'set_property -help' for usage info.<br/>
/// set_property -name {XELAB.MORE_OPTIONS} -value {-pulse_e_style ondetect}\<br/>
/// -objects [get_filesets sim_1]<br/>
/// The following example sets the internal VREF property value for the specified IO Bank:<br/>
/// set_property internal_vref {0.75} [get_iobanks 0]<br/>
/// The following example defines a DCI Cascade by setting the DCI_CASCADE property for the<br/>
/// specified IO Bank:<br/>
/// set_property DCI_CASCADE {14} [get_iobanks 0 ]<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// The following example configures the synth_1 run, setting options for Vivado Synthesis 2013,<br/>
/// and then launches the synthesis run:<br/>
/// set_property flow {Vivado Synthesis 2016} \<br/>
/// [get_runs synth_1]<br/>
/// set_property STEPS.SYNTH_DESIGN.ARGS.GATED_CLOCK_CONVERSION on \<br/>
/// [get_runs synth_1]<br/>
/// set_property STEPS.SYNTH_DESIGN.ARGS.FSM_EXTRACTION one_hot \<br/>
/// [get_runs synth_1]<br/>
/// launch_runs synth_1<br/>
/// This example is the same as the prior example, except that it uses the -dict option to set all the<br/>
/// properties on the synthesis run in a single set_property command:<br/>
/// set_property -dict [ list flow {Vivado Synthesis 2016} \<br/>
/// STEPS.SYNTH_DESIGN.ARGS.GATED_CLOCK_CONVERSION on \<br/>
/// STEPS.SYNTH_DESIGN.ARGS.FSM_EXTRACTION \<br/>
/// one_hot ] [get_runs synth_1]<br/>
/// launch_runs synth_1<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1682<br/>
/// </para>
/// </summary>
/// <param name="name">(Required) Name of property to set. Not valid with -dict option</param>
/// <param name="value">(Required) Value of property to set. Not valid with -dict option</param>
/// <param name="objects">(Required) Objects to set properties on</param>
/// <param name="dict">(Optional) list of name/value pairs of properties to set</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL set_property(TCLObject name, TCLObject value, TCLObjectList objects, TCLParameterList dict = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: set_property [-dict <args>] [-quiet] [-verbose] <name> <value> <objects>...
_tcl.Entry(_builder.set_property(name, value, objects, dict, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Reset property on object(s)<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: reset_property [-quiet] [-verbose] <property_name> <objects>...
/// <br/>
/// <para>
/// Restores the specified property to its default value on the specified object or objects. If no<br/>
/// default is defined for the property, the property is unassigned on the specified object.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example sets the DOB_REG property on the specified Block RAM, and then resets<br/>
/// the property:<br/>
/// set_property DOB_REG 1 [get_cells usbEngine1/usbEngineSRAM/<br/>
/// snoopyRam_reg_19]<br/>
/// reset_property DOB_REG [get_cells usbEngine1/usbEngineSRAM/snoopyRam_reg_19]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1511<br/>
/// </para>
/// </summary>
/// <param name="property_name">(Required) Name of property to reset</param>
/// <param name="objects">(Required) Objects to set properties</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <returns>The value that was set if success, "" if failure</returns>
public TTCL reset_property(TCLObject property_name, TCLObjectList objects, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: reset_property [-quiet] [-verbose] <property_name> <objects>...
_tcl.Entry(_builder.reset_property(property_name, objects, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Add cells to a Pblock<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: add_cells_to_pblock [-top] [-add_primitives] [-clear_locs] [-quiet] [-verbose] <pblock> [<cells>...]
/// <br/>
/// <para>
/// Adds specified logic instances to a Pblock in an open implemented design. Once cells have been<br/>
/// added to a Pblock, you can place the Pblocks onto the fabric of the FPGA using the<br/>
/// resize_pblock command. The resize_pblock command can also be used to manually<br/>
/// move and resize Pblocks.<br/>
/// You can remove instances from the Pblock using the remove_cells_from_pblock command.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example creates a Pblock called pb_cpuEngine, and then adds only the leaf-cells<br/>
/// found in the cpuEngine module, clearing placement constraints for placed instances:<br/>
/// create_pblock pb_cpuEngine<br/>
/// add_cells_to_pblock pb_cpuEngine [get_cells cpuEngine/*] \<br/>
/// -add_primitives -clear_locs<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 35<br/>
/// </para>
/// </summary>
/// <param name="pblock">(Required) Pblock to add cells to</param>
/// <param name="top">
/// <para>
/// (Optional)<br/>
/// Add the top level instance; This option can't be used with -<br/>
/// cells, or -add_primitives options. You must specify either -<br/>
/// cells or -top option.<br/>
/// </para>
/// </param>
/// <param name="add_primitives">
/// <para>
/// (Optional)<br/>
/// Assign to the pblock only primitive cells from the specified<br/>
/// list of cells.<br/>
/// </para>
/// </param>
/// <param name="clear_locs">(Optional) Clear instance location constraints</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="cells">
/// <para>
/// (Optional)<br/>
/// Cells to add. You can't use this option with -top option. You<br/>
/// must specify either -cells or -top option.<br/>
/// </para>
/// </param>
public TTCL add_cells_to_pblock(TCLObject pblock, bool?top = null, bool?add_primitives = null, bool?clear_locs = null, bool?quiet = null, bool?verbose = null, TCLObjectList cells = null)
{
// TCL Syntax: add_cells_to_pblock [-top] [-add_primitives] [-clear_locs] [-quiet] [-verbose] <pblock> [<cells>...]
_tcl.Entry(_builder.add_cells_to_pblock(pblock, top, add_primitives, clear_locs, quiet, verbose, cells));
return(_tcl);
}
/// <summary>
/// <para>
/// Unplace one or more instances.<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: unplace_cell [-quiet] [-verbose] <cell_list>...
/// <br/>
/// <para>
/// Unplace the specified cells from their current placement site.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example unplaces the specified cell:<br/>
/// unplace_cell {fftEngine/fftInst/ingressLoop[6].ingressFifo/buffer_fifo/<br/>
/// i_4773_12897}<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// The following example unplaces multiple cells:<br/>
/// unplace_cell {div_cntr_reg_inferredi_4810_15889 div_cntr_reg[0]<br/>
/// div_cntr_reg[1]}<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1754<br/>
/// </para>
/// </summary>
/// <param name="cell_list">(Required) a list of cells to be unplaced</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL unplace_cell(TCLObjectList cell_list, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: unplace_cell [-quiet] [-verbose] <cell_list>...
_tcl.Entry(_builder.unplace_cell(cell_list, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Remove cells from a Pblock<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: remove_cells_from_pblock [-quiet] [-verbose] <pblock> <cells>...
/// <br/>
/// <para>
/// Removes the specified logic instances from a Pblock. Cells are added to a Pblock with the<br/>
/// add_cells_to_pblock command.<br/>
/// Note: Cells that have been placed will not be unplaced as they are removed from a Pblock. Any current<br/>
/// LOC assignments are left intact.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example removes the specified cells from the pb_cpuEngine Pblock:<br/>
/// remove_cells_from_pblock pb_cpuEngine [get_cells cpuEngine/cpu_dwb_dat_o/*]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1237<br/>
/// </para>
/// </summary>
/// <param name="pblock">(Required) Pblock to remove cells from</param>
/// <param name="cells">(Required) Cells to remove</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL remove_cells_from_pblock(TCLObject pblock, TCLObjectList cells, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: remove_cells_from_pblock [-quiet] [-verbose] <pblock> <cells>...
_tcl.Entry(_builder.remove_cells_from_pblock(pblock, cells, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Create pins in the current design<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: create_pin [-from <arg>] [-to <arg>] -direction <arg> [-quiet] [-verbose] <pins>...
/// <br/>
/// <para>
/// Add single pins or bus pins to the current netlist of an open Synthesized or Implemented Design.<br/>
/// You may define attributes of the pin such as direction and bus width, as well as the pin name.<br/>
/// Bus pins can be created with increasing or decreasing bus indexes, using negative and positive<br/>
/// index values.<br/>
/// The pins must be created on an existing cell instance, or it is considered a top-level pin which<br/>
/// should be created using the create_port command. If the instance name of a cell is not<br/>
/// specified as part of the pin name, an error will be returned.<br/>
/// Note: You cannot add pins to library macros, or macro-primitives.<br/>
/// Netlist editing changes the in-memory view of the netlist in the current design. It does not<br/>
/// change the files in the source fileset, or change the persistent design on the disk. Changes made<br/>
/// to the netlist may be saved to a design checkpoint using the write_checkpoint command, or<br/>
/// may be exported to a netlist file such as Verilog, VHDL, or EDIF, using the appropriate write_*<br/>
/// command.<br/>
/// Note: Netlist editing is not allowed on the elaborated RTL design.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following example creates a new input pin on the cpuEngine module with the specified pin<br/>
/// name:<br/>
/// create_pin -direction IN cpuEngine/inPin<br/>
/// The following example sets the hierarchy separator, creates a new black box instance of the<br/>
/// reference cell, and creates a twenty-four bit bidirectional bus for that instance:<br/>
/// set_hierarchy_separator |<br/>
/// create_cell -reference dmaBlock -black_box usbEngine0|myDMA<br/>
/// create_pin -direction INOUT -from 0 -to 23 usbEngine0|myDMA|dataBus<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 332<br/>
/// </para>
/// </summary>
/// <param name="direction">(Required) Pin direction Values: IN, OUT, INOUT</param>
/// <param name="pins">(Required) Names of pins to create</param>
/// <param name="from">(Optional) Starting bus index</param>
/// <param name="to">(Optional) Ending bus index</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL create_pin(create_pin_direction direction, TCLObjectList pins, String from = null, String to = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: create_pin [-from <arg>] [-to <arg>] -direction <arg> [-quiet] [-verbose] <pins>...
_tcl.Entry(_builder.create_pin(direction, pins, from, to, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Remove cells from the current design<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: remove_cell [-quiet] [-verbose] <cells>...
/// <br/>
/// <para>
/// Remove cells from the current netlist in either an open Synthesized or Implemented design.<br/>
/// Note: You cannot remove cells from library macros, also called macro-primitives.<br/>
/// Netlist editing changes the in-memory view of the netlist in the current design. It does not<br/>
/// change the files in the source fileset, or change the persistent design on the disk. Changes made<br/>
/// to the netlist may be saved to a design checkpoint using the write_checkpoint command, or<br/>
/// may be exported to a netlist file such as Verilog, VHDL, or EDIF, using the appropriate write_*<br/>
/// command.<br/>
/// Note: Netlist editing is not allowed on the elaborated RTL design.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example removes the fftEngine from the in-memory netlist of the current design:<br/>
/// remove_cell fftEngine<br/>
/// remove_cell usbEngine0/usb_out<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1235<br/>
/// </para>
/// </summary>
/// <param name="cells">(Required) List of cells to remove</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL remove_cell(TCLObjectList cells, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: remove_cell [-quiet] [-verbose] <cells>...
_tcl.Entry(_builder.remove_cell(cells, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Remove one or more custom commands<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: remove_gui_custom_commands [-quiet] [-verbose] <names>...
/// <br/>
/// <para>
/// Remove one or more GUI custom commands.<br/>
/// You can use the get_gui_custom_commands to determine the list of defined custom<br/>
/// commands.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example removes the GUI custom commands with names 'abc' and 'xyz':<br/>
/// remove_gui_custom_commands {abc xyz}<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1254<br/>
/// </para>
/// </summary>
/// <param name="names">(Required) name of one or more custom commands to remove</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL remove_gui_custom_commands(TCLObjectList names, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: remove_gui_custom_commands [-quiet] [-verbose] <names>...
_tcl.Entry(_builder.remove_gui_custom_commands(names, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// rename a cell<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: rename_cell -to <arg> [-quiet] [-verbose] <cell>...
/// <br/>
/// <para>
/// Rename a single hierarchical or leaf-level cell in the current synthesized or implemented design.<br/>
/// TIP: You cannot rename cells with DONT_TOUCH property set to TRUE.<br/>
/// Netlist editing changes the in-memory view of the netlist in the current design. It does not<br/>
/// change the files in the source fileset, or change the persistent design on the disk. Changes made<br/>
/// to the netlist may be saved to a design checkpoint using the write_checkpoint command, or<br/>
/// may be exported to a netlist file such as Verilog, VHDL, or EDIF, using the appropriate write_*<br/>
/// command.<br/>
/// Note: Netlist editing is not allowed on the elaborated RTL design.<br/>
/// Changes to the names of cells, nets, pins, and ports, will also affect the design constraints defined<br/>
/// in the in-memory design. Constraints are automatically modified to target the new object name,<br/>
/// however these are not written back to the source XDC file. Saving the modified in-memory<br/>
/// design using write_checkpoint will save both the renamed objects and modified constraints.<br/>
/// This command returns nothing if successful, or an error if it fails.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following example changes the name of the hierarchical or1200_cpu cell as specified:<br/>
/// rename_cell -to or1200_gpu or1200_cpu<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1275<br/>
/// </para>
/// </summary>
/// <param name="to">(Required) New name</param>
/// <param name="cell">(Required) Cell to rename</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL rename_cell(String to, TCLObjectList cell, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: rename_cell -to <arg> [-quiet] [-verbose] <cell>...
_tcl.Entry(_builder.rename_cell(to, cell, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Connect nets and pins to debug port channels<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: connect_debug_port [-channel_start_index <arg>] [-quiet] [-verbose] <port> <nets>...
/// <br/>
/// <para>
/// Connects a signal from the netlist design to a port on an ILA debug core that was added to the<br/>
/// design using the create_debug_core command. The signal can either be connected to a<br/>
/// specific channel index on the port, or simply connected to an available channel on the port.<br/>
/// If you try to connect too many signals to a port, or there are not enough channels to support the<br/>
/// connection, the tool will return an error.<br/>
/// Additional ports can be added to a debug core through the use of the create_debug_port<br/>
/// command, and you can increase the available channels on an existing port with the<br/>
/// set_property port_width command. See the examples below.<br/>
/// You can disconnect signals from ports using the disconnect_debug_port command.<br/>
/// When the debug core has been defined and connected, you can implement the debug core as a<br/>
/// block for inclusion in the netlist design. Use the implement_debug_core command to<br/>
/// implement the core.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// The following example creates a new PROBE port on the myCore debug core, increases the<br/>
/// PORT_WIDTH property of the port in order to prepare it to receive the number of signals to be<br/>
/// connected, and connects signals to the port starting at the third channel position (index 2).<br/>
/// create_debug_port myCore PROBE<br/>
/// set_property PORT_WIDTH 8 [get_debug_ports myCore/PROBE1]<br/>
/// connect_debug_port myCore/PROBE1 [get_nets [list m0_ack_o m0_cyc_i \<br/>
/// m0_err_o m0_rty_o m0_stb_i m0_we_i ]] -channel_start_index 2<br/>
/// Note: If you specify too many nets to connect to the available channels on the port, the tool will return an<br/>
/// error and will not connect the ports.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 201<br/>
/// </para>
/// </summary>
/// <param name="port">(Required) Debug port name</param>
/// <param name="nets">(Required) List of nets or pins</param>
/// <param name="channel_start_index">(Optional) Connect nets starting at channel index</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL connect_debug_port(TCLObject port, TCLObjectList nets, String channel_start_index = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: connect_debug_port [-channel_start_index <arg>] [-quiet] [-verbose] <port> <nets>...
_tcl.Entry(_builder.connect_debug_port(port, nets, channel_start_index, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Delete one or more DRC/METHODOLOGY/CDC message waivers<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: delete_waivers [-scoped] [-quiet] [-verbose] [<objects>...]
/// <br/>
/// <para>
/// After report_drc, report_methodology, or report_cdc commands are run, they return<br/>
/// messages of specific violations or conditions found in the design. These violations can prevent<br/>
/// the design from progressing until they have been resolved or addressed in some way. The<br/>
/// create_waiver command lets you select individual violations or specific checks that can be<br/>
/// waived for a design, letting you move forward in the design flow.<br/>
/// Use the delete_waivers command to remove waivers from the design.<br/>
/// </para>
/// <br/>
/// <para>
/// This example deletes all the DRC waivers in the design:<br/>
/// delete_waivers [get_waivers -type DRC]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 484<br/>
/// </para>
/// </summary>
/// <param name="scoped">
/// <para>
/// (Optional)<br/>
/// flag waiver to interpret object wildcards as scoped to the<br/>
/// current_instance that is set<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="objects">
/// <para>
/// (Optional)<br/>
/// List of waiver objects, or a list of message objects (cells,<br/>
/// nets, sites, etc.) for which DRC/METHODOLOGY waiver(s)<br/>
/// were set<br/>
/// </para>
/// </param>
public TTCL delete_waivers(bool?scoped = null, bool?quiet = null, bool?verbose = null, TCLObjectList objects = null)
{
// TCL Syntax: delete_waivers [-scoped] [-quiet] [-verbose] [<objects>...]
_tcl.Entry(_builder.delete_waivers(scoped, quiet, verbose, objects));
return(_tcl);
}
/// <summary>
/// <para>
/// Delete a debug core<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: delete_debug_core [-quiet] [-verbose] <cores>...
/// <br/>
/// <para>
/// Removes Vivado Lab Edition debug cores from the current project that were added by the<br/>
/// create_debug_core command.<br/>
/// </para>
/// <br/>
/// <para>
/// The following command deletes the myCore debug core from the current project:<br/>
/// delete_debug_core myCore<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// The following command deletes all debug cores from the current project:<br/>
/// delete_debug_core [get_debug_cores]<br/>
/// Note: The get_debug_cores command returns all debug cores as a default.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 434<br/>
/// </para>
/// </summary>
/// <param name="cores">(Required) Debug cores to delete</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL delete_debug_core(TCLObjectList cores, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: delete_debug_core [-quiet] [-verbose] <cores>...
_tcl.Entry(_builder.delete_debug_core(cores, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Set switching activity on specified objects or default types<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: set_switching_activity [-toggle_rate <arg>] [-default_toggle_rate <arg>] [-type <args>] [-all] [-static_probability <arg>] [-default_static_probability <arg>] [-signal_rate <arg>] [-hier] [-deassert_resets] [-quiet] [-verbose] [<objects>...]
/// <br/>
/// <para>
/// Sets the signal rate and the switching probability to be used when performing power estimation<br/>
/// on the current synthesized or implemented design. These include simple signal rate and simple<br/>
/// static probability on nets, ports, and pins; and state dependent static probabilities on cells.<br/>
/// Note: This command operates silently and does not return direct feedback of its operation.<br/>
/// The switching activity of a design affects both the static and dynamic power consumption. The<br/>
/// static power is often dependent on logic state transitions, and the dynamic power is directly<br/>
/// proportional to the toggle rate.<br/>
/// The set_switching_activity command can be used to specify default activity rates for the<br/>
/// whole design, or to define the activity of one or more signals in the design or on a specified<br/>
/// module.<br/>
/// The current switching activity attributes can be found by using the<br/>
/// report_switching_activity command. The values can be set to their default values by<br/>
/// using the reset_switching_activity command.<br/>
/// Note: The reset_switching_activity is used to reset switching activity for specified objects. Use the<br/>
/// set_switching_activity -default_toggle_rate or -default_static_probability to<br/>
/// change or reset these values.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example specifies a signal rate and switching probability for all ports, then reports<br/>
/// the switching attributes for those ports:<br/>
/// set_switching_activity -signal_rate 55 -static_probability .33 [get_ports]<br/>
/// report_switching_activity [get_ports]<br/>
/// The following example specifies the default switching probability for the current design:<br/>
/// set_switching_activity -default_static_probability .75<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// This example sets the specified toggle rate and static probability on all registers in the hierarchy<br/>
/// of "CPU/MEM":<br/>
/// set_switching_activity -type register -toggle_rate 0.4 \<br/>
/// -static_probability 0.5 [get_cells CPU/MEM]<br/>
/// This example sets the specified toggle rate and static probability on all registers in the hierarchy<br/>
/// of "CPU/" and underneath hierarchy:<br/>
/// set_switching_activity -type register -toggle_rate 0.4<br/>
/// -static_probability 0.5 -hier [get_cells CPU]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1688<br/>
/// </para>
/// </summary>
/// <param name="toggle_rate">
/// <para>
/// (Optional)<br/>
/// Toggle rate (%) is the rate at which the output of<br/>
/// synchronous logic element switches compared to a given<br/>
/// clock input. It is modeled as a percentage between 0 - 200%.<br/>
/// A toggle rate of 100% means that on average the output<br/>
/// toggles once during every clock cycle, changing on either<br/>
/// the rising or falling clock edges, and making the effective<br/>
/// output signal frequency half of the clock frequency. Default:<br/>
/// 0.0<br/>
/// </para>
/// </param>
/// <param name="default_toggle_rate">
/// <para>
/// (Optional)<br/>
/// The default toggle rate to be used in power analysis on the<br/>
/// primary inputs of the design. The default toggle rate is set<br/>
/// on those primary input nets whose switching activity is not<br/>
/// specified by the user, simulation data or constraints of the<br/>
/// design. Valid values are: 0 <= value < 200. The default value<br/>
/// is 12.5. Default: 12.5<br/>
/// </para>
/// </param>
/// <param name="type">
/// <para>
/// (Optional)<br/>
/// Specify nodes in a specific category. List of valid type values:<br/>
/// io_output, io_bidir_enable, register, lut_ram, lut, dsp,<br/>
/// bram_enable, bram_wr_enable, gt_txdata, gt_rxdata.<br/>
/// </para>
/// </param>
/// <param name="all">
/// <para>
/// (Optional)<br/>
/// Used together with -type, set switching activity on -type nets<br/>
/// within an instance<br/>
/// </para>
/// </param>
/// <param name="static_probability">(Optional) Static probability value: 0 <= Value <= 1 Default: 0.5</param>
/// <param name="default_static_probability">
/// <para>
/// (Optional)<br/>
/// The default static probability to be used in power analysis<br/>
/// on the design. The default static probability is set on those<br/>
/// primary inputs whose switching activity is not specified by<br/>
/// the user, simulation data or constraints of the design. Valid<br/>
/// values are: 0 <= Value <= 1. The default value is 0.5. Default:<br/>
/// 0.5<br/>
/// </para>
/// </param>
/// <param name="signal_rate">
/// <para>
/// (Optional)<br/>
/// The number of times an element changed state (high-to-low<br/>
/// and low-to-high) per second. Xilinx tools express this as<br/>
/// millions of transitions per second (Mtr/s). Default: 0.0<br/>
/// </para>
/// </param>
/// <param name="hier">
/// <para>
/// (Optional)<br/>
/// Hierarchically sets the switching activity on a hierarchical<br/>
/// instance provided via <objects> option. This option should<br/>
/// be used only with <objects> option<br/>
/// </para>
/// </param>
/// <param name="deassert_resets">
/// <para>
/// (Optional)<br/>
/// A switch to elegantly auto deassert all set,reset,preset and<br/>
/// clear signals that do not have conflicted polarities<br/>
/// </para>
/// </param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="objects">
/// <para>
/// (Optional)<br/>
/// Objects to set switching activity on<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// </param>
public TTCL set_switching_activity(String toggle_rate = null, String default_toggle_rate = null, TCLParameterList type = null, bool?all = null, String static_probability = null, String default_static_probability = null, Int32?signal_rate = null, bool?hier = null, bool?deassert_resets = null, bool?quiet = null, bool?verbose = null, TCLObjectList objects = null)
{
// TCL Syntax: set_switching_activity [-toggle_rate <arg>] [-default_toggle_rate <arg>] [-type <args>] [-all] [-static_probability <arg>] [-default_static_probability <arg>] [-signal_rate <arg>] [-hier] [-deassert_resets] [-quiet] [-verbose] [<objects>...]
_tcl.Entry(_builder.set_switching_activity(toggle_rate, default_toggle_rate, type, all, static_probability, default_static_probability, signal_rate, hier, deassert_resets, quiet, verbose, objects));
return(_tcl);
}
/// <summary>
/// <para>
/// Implement debug core<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: implement_debug_core [-quiet] [-verbose] [<cores>...]
/// <br/>
/// <para>
/// Implements the Vivado logic analyzer debug cores in the current project. The tools will be run<br/>
/// once for any ILA debug cores specified, and run one more time for the Debug Hub core if all<br/>
/// cores are specified. The ILA core (labtools_ila_v3) is the only core type currently supported by the<br/>
/// create_debug_core command. The tool automatically adds a Debug Hub core<br/>
/// (labtools_xsdbmasterlib_v2) to contain and configure the ILA cores in the project.<br/>
/// The Vivado tool creates Debug Hub core and ILA cores initially as black boxes. These cores must<br/>
/// be implemented prior to running through place and route. After the core is created with<br/>
/// create_debug_core, and while ports are being added and connected with<br/>
/// create_debug_port and connect_debug_port, the content of the debug core is not<br/>
/// defined or visible within the design.<br/>
/// Debug core implementation is automatic when you launch an implementation run using the<br/>
/// launch_runs command, or during design optimization using opt_design. However, you can<br/>
/// also use the implement_debug_core command to implement one or more of the cores in the<br/>
/// design without having to implement the whole design.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example implements all debug cores in the current project:<br/>
/// implement_debug_core [get_debug_cores]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 978<br/>
/// </para>
/// </summary>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="cores">(Optional) Debug core</param>
public TTCL implement_debug_core(bool?quiet = null, bool?verbose = null, TCLObjectList cores = null)
{
// TCL Syntax: implement_debug_core [-quiet] [-verbose] [<cores>...]
_tcl.Entry(_builder.implement_debug_core(quiet, verbose, cores));
return(_tcl);
}
/// <summary>
/// <para>
/// Automatically place a set of ports<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: place_ports [-skip_unconnected_ports] [-check_only] [-iobank <args>] [-quiet] [-verbose] [<ports>...]
/// <br/>
/// <para>
/// Assign ports to the pins of the Xilinx FPGA package, by automatically or manually placing ports.<br/>
/// • Automatically places ports on an available I/O or clocking site, or into the specified I/O banks.<br/>
/// • Manually assigns ports to the specified package_pin when both the port and pin are specified.<br/>
/// The place_ports command will not replace ports that are currently placed by the user, or<br/>
/// ports that are placed and fixed.<br/>
/// Note: This command operates silently and does not return direct feedback of its operation.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example places the port objects returned by the get_ports command, onto I/O<br/>
/// bank 13 of the device, as returned by get_iobanks:<br/>
/// place_ports -iobank [get_iobanks 13] [get_ports DataOut_pad_1_o]<br/>
/// The follow example uses port_name package_pin pairs to manually place multiple ports:<br/>
/// place_ports {LEDS_n[2] AA11 LEDS_n[3] AA10 LEDS_n[0] Y11 LEDS_n[1] Y10}<br/>
/// The following example places all input ports onto I/O banks 12, 13, 14 and 15 of the device:<br/>
/// place_ports -iobank [get_iobanks {12 13 14 15}] [all_inputs]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1129<br/>
/// </para>
/// </summary>
/// <param name="skip_unconnected_ports">(Optional) Do not place unconnected ports</param>
/// <param name="check_only">(Optional) Only check IO/Clock placement DRCs</param>
/// <param name="iobank">(Optional) Limit placement to the following banks</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
/// <param name="ports">
/// <para>
/// (Optional)<br/>
/// Ports to place (if omitted, all ports will be placed). If the<br/>
/// arguments are interleaved objects of ports and package<br/>
/// pins, then manual placement is performed<br/>
/// </para>
/// </param>
public TTCL place_ports(bool?skip_unconnected_ports = null, bool?check_only = null, TCLParameterList iobank = null, bool?quiet = null, bool?verbose = null, TCLObjectList ports = null)
{
// TCL Syntax: place_ports [-skip_unconnected_ports] [-check_only] [-iobank <args>] [-quiet] [-verbose] [<ports>...]
_tcl.Entry(_builder.place_ports(skip_unconnected_ports, check_only, iobank, quiet, verbose, ports));
return(_tcl);
}
/// <summary>
/// <para>
/// Reset one or more Methodology checks to factory defaults.<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: reset_methodology_check [-quiet] [-verbose] [<checks>...]
/// <br/>
/// <para>
/// Reset the specified methodology checks to the defaults provided by the Vivado Design Suite.<br/>
/// This will restore the check to its default configuration, including any changes to the IS_ENABLED<br/>
/// or SEVERITY properties.<br/>
/// The IS_ENABLED property can be modified on a specific methodology check to disable the rule<br/>
/// from being checked, even when it is specified directly in the report_methodology command.<br/>
/// The SEVERITY property is an enumerated property that can be modified to change the severity<br/>
/// associated with a specific methodology check when a violation is found during the<br/>
/// report_methodology command. The supported values are: FATAL, ERROR, "CRITICAL<br/>
/// WARNING", WARNING, ADVISORY<br/>
/// </para>
/// <br/>
/// <para>
/// The following example modifies the IS_ENABLED and SEVERITY properties for the CHECK-4<br/>
/// methodology check, reports the properties of the check to see the changes, and then resets the<br/>
/// methodology check to its default setting:<br/>
/// set_property IS_ENABLED false [get_methodology_checks CHECK-4]<br/>
/// set_property SEVERITY Warning [get_methodology_checks CHECK-4]<br/>
/// report_property [get_methodology_checks CHECK-4]<br/>
/// reset_methodology_check [get_methodology_checks CHECK-4]<br/>
/// report_property [get_methodology_checks CHECK-4]<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1496<br/>
/// </para>
/// </summary>
/// <param name="checks">(Required) The list of checks to reset.</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL reset_methodology_check(TCLObjectList checks, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: reset_methodology_check [-quiet] [-verbose] [<checks>...]
_tcl.Entry(_builder.reset_methodology_check(checks, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Resize port bus in the current design<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: resize_port_bus [-from <arg>] [-to <arg>] [-quiet] [-verbose] <port_bus_name>...
/// <br/>
/// <para>
/// Resize an existing bus port, to grow the bus, shrink the bus, or renumber the current range of<br/>
/// port indexes. You can only do a single grow, shrink, or renumber operation with each command.<br/>
/// • You can grow the bus by indicating a new range of port indexes outside the current range of<br/>
/// indexes. Growing the bus leaves existing port indexes connected as they currently are.<br/>
/// • You can shrink the bus by indicating a new range of port indexes inside the current range of<br/>
/// indexes. Shrinking the bus, eliminates connections to removed bus ports, but leaves the<br/>
/// remaining ports connected as they currently are.<br/>
/// • You can renumber the current bus indexes by providing a new range of port indexes with the<br/>
/// same width as the current range. Renumbering ports changes the port index, but does not<br/>
/// otherwise change connections.<br/>
/// Netlist editing changes the in-memory view of the netlist in the current design. It does not<br/>
/// change the files in the source fileset, or change the persistent design on the disk. Changes made<br/>
/// to the netlist may be saved to a design checkpoint using the write_checkpoint command, or<br/>
/// may be exported to a netlist file such as Verilog, VHDL, or EDIF, using the appropriate write_*<br/>
/// command.<br/>
/// Note: Netlist editing is not allowed on the elaborated RTL design.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// This command returns nothing if successful, and returns an error if it fails.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example creates a 32-bit output bus port, then renumbers the ports to include<br/>
/// negative bus indexes, then shrinks the bus width from 32-bits to 16-bits:<br/>
/// create_port -direction out -from 0 -to 31 outPorts<br/>
/// resize_port_bus -from -16 -to 15 outPorts<br/>
/// resize_port_bus -from -8 -to 7 outPorts<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1533<br/>
/// </para>
/// </summary>
/// <param name="port_bus_name">(Required) Name of the port bus to resize</param>
/// <param name="from">(Optional) New starting bus index</param>
/// <param name="to">(Optional) New ending bus index</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL resize_port_bus(TCLObjectList port_bus_name, String from = null, String to = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: resize_port_bus [-from <arg>] [-to <arg>] [-quiet] [-verbose] <port_bus_name>...
_tcl.Entry(_builder.resize_port_bus(port_bus_name, from, to, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Create cells in the current design<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: create_cell -reference <arg> [-black_box] [-quiet] [-verbose] <cells>...
/// <br/>
/// <para>
/// Add cells to the netlist of the current Synthesized or Implemented design.<br/>
/// Note: You cannot add cells to library macros, or macro-primitives.<br/>
/// New cell instances can be added to the top-level of the design, or hierarchically within any<br/>
/// module of the design. Instances can reference an existing cell from the library or design source<br/>
/// files, or a black box instance can be added that reference cells that have not yet been created.<br/>
/// Netlist editing changes the in-memory view of the netlist in the current design. It does not<br/>
/// change the files in the source fileset, or change the persistent design on the disk. Changes made<br/>
/// to the netlist may be saved to a design checkpoint using the write_checkpoint command, or<br/>
/// may be exported to a netlist file such as Verilog, VHDL, or EDIF, using the appropriate write_*<br/>
/// command.<br/>
/// Note: Netlist editing is not allowed on the elaborated RTL design.<br/>
/// This command returns the name of the created cell instance or instances.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example creates three new cell instances of the or1200_cpu module with the<br/>
/// specified instance names:<br/>
/// create_cell -reference or1200_cpu myCell1 myCell2 myCell3<br/>
/// The following example sets the hierarchy separator character, then creates a black box instance<br/>
/// for the referenced cell, specifying a hierarchical instance name:<br/>
/// set_hierarchy_separator |<br/>
/// create_cell -reference dmaBlock -black_box usbEngine0|myDMA<br/>
/// Note: The tool will return an error when -black_box is used, but the -reference cell already exists.<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 243<br/>
/// </para>
/// </summary>
/// <param name="reference">(Required) Library cell or design which cells reference</param>
/// <param name="cells">(Required) Names of cells to create</param>
/// <param name="black_box">(Optional) Create black box instance</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL create_cell(String reference, TCLObjectList cells, bool?black_box = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: create_cell -reference <arg> [-black_box] [-quiet] [-verbose] <cells>...
_tcl.Entry(_builder.create_cell(reference, cells, black_box, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Remove differential pair relationship between 2 ports<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: split_diff_pair_ports [-quiet] [-verbose] <ports>...
/// <br/>
/// <para>
/// Splits an existing differential pair of ports into two single-ended ports.<br/>
/// Note: This command operates silently and does not return direct feedback of its operation.<br/>
/// </para>
/// <br/>
/// <para>
/// The following example splits the specified diff pair ports to form two single ended ports:<br/>
/// split_diff_pair_ports PORT_N PORT_P<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 1711<br/>
/// </para>
/// </summary>
/// <param name="ports">(Required) Ports to split</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL split_diff_pair_ports(TCLObjectList ports, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: split_diff_pair_ports [-quiet] [-verbose] <ports>...
_tcl.Entry(_builder.split_diff_pair_ports(ports, quiet, verbose));
return(_tcl);
}
/// <summary>
/// <para>
/// Create nets in the current design<br/>
/// </para>
/// <br/>
/// <br/>
/// TCL Syntax: create_net [-from <arg>] [-to <arg>] [-quiet] [-verbose] <nets>...
/// <br/>
/// <para>
/// Create new nets in the current netlist of an open Synthesized or Implemented Design.<br/>
/// Note: You cannot add nets to library macros, or macro-primitives.<br/>
/// Nets can be created hierarchically from the top-level of the design, or within any level of the<br/>
/// hierarchy by specifying the hierarchical net name.<br/>
/// Bus nets can be created with increasing or decreasing bus indexes, using negative and positive<br/>
/// index values.<br/>
/// New nets are unconnected in the netlist at the time of creation. You must connect nets as<br/>
/// desired using the connect_net command. Connected nets can be unconnected using the<br/>
/// disconnect_net command, and can be removed from the netlist using the remove_net<br/>
/// command.<br/>
/// Netlist editing changes the in-memory view of the netlist in the current design. It does not<br/>
/// change the files in the source fileset, or change the persistent design on the disk. Changes made<br/>
/// to the netlist may be saved to a design checkpoint using the write_checkpoint command, or<br/>
/// may be exported to a netlist file such as Verilog, VHDL, or EDIF, using the appropriate write_*<br/>
/// command.<br/>
/// Note: Netlist editing is not allowed on the elaborated RTL design.<br/>
/// UG835 (v2020.2) November 18, 2020 www.xilinx.com<br/>
/// </para>
/// <br/>
/// <para>
/// See ug835-vivado-tcl-commands.pdf, page 323<br/>
/// </para>
/// </summary>
/// <param name="nets">(Required) Names of nets to create</param>
/// <param name="from">(Optional) Starting bus index</param>
/// <param name="to">(Optional) Ending bus index</param>
/// <param name="quiet">(Optional) Ignore command errors</param>
/// <param name="verbose">(Optional) Suspend message limits during command execution</param>
public TTCL create_net(TCLObjectList nets, String from = null, String to = null, bool?quiet = null, bool?verbose = null)
{
// TCL Syntax: create_net [-from <arg>] [-to <arg>] [-quiet] [-verbose] <nets>...
_tcl.Entry(_builder.create_net(nets, from, to, quiet, verbose));
return(_tcl);
}
