public void Add(string signalName, int width, PortMapper.MappingKind mappingKind) { if (m_signals.ContainsKey(signalName)) { throw new ArgumentException("Entity signal " + signalName + " exists already"); } m_signals[signalName] = width; m_mappings[signalName] = mappingKind; }
public override string ToString() { StringBuilder buffer = new StringBuilder(); // we need signalWidths as a list ... List <KeyValuePair <string, int> > interfaceSignals = new List <KeyValuePair <string, int> >(); foreach (KeyValuePair <string, int> tupel in m_signals) { interfaceSignals.Add(tupel); } for (int i = 0; i < interfaceSignals.Count; i++) { string signalName = interfaceSignals[i].Key; string line = ""; PortMapper.MappingKind mappingKind = m_mappings.ContainsKey(signalName) ? m_mappings[signalName] : PortMapper.MappingKind.External; if (mappingKind == PortMapper.MappingKind.NoVector) { line = "\t" + signalName + " : " + m_directions[signalName].ToString().ToLower() + " std_logic"; } else { line = "\t" + signalName + " : " + m_directions[signalName].ToString().ToLower() + " std_logic_vector(" + (interfaceSignals[i].Value - 1) + " downto 0)"; } // ... to find the last index if (i < interfaceSignals.Count - 1) { line += ";"; } else { line += ");"; } buffer.AppendLine(line); } return(buffer.ToString()); }
protected override void DoCommandAction() { OutputManager.WriteOutput("# e.g. expect outpin left_3 SLICE_X5Y83 CMUX static_to_partial 5 -> expect vector index 5 in netname"); OutputManager.WriteOutput("# e.g. expect outpin left_5 SLICE_X342Y283 AMUX static_to_partial x -> no vector"); foreach (LibElemInst inst in LibraryElementInstanceManager.Instance.GetAllInstantiations().Where(i => Regex.IsMatch(i.InstanceName, InstantiationFilter))) { LibraryElement libElement = Objects.Library.Instance.GetElement(inst.LibraryElementName); OutputManager.WriteOutput("# expected ports for instance " + inst.InstanceName + " (instance of " + libElement.Name + ")"); foreach (XDLPort port in libElement.Containter.Ports) { // only consider external ports bool hasKindMapping = inst.PortMapper.HasKindMapping(port.ExternalName); if (hasKindMapping) { PortMapper.MappingKind mappingKind = inst.PortMapper.GetMapping(port.ExternalName); if (mappingKind != PortMapper.MappingKind.External) { continue; } } bool hasMapping = inst.PortMapper.HasSignalMapping(port.ExternalName); string inoutPin = port.Direction == FPGA.FPGATypes.PortDirection.In ? "inpin" : "outpin"; string portName = hasMapping ? inst.PortMapper.GetSignalName(port.ExternalName) : "unknown"; string index = inst.PortMapper.HasIndex(port.ExternalName) ? inst.PortMapper.GetIndex(port.ExternalName).ToString() : "-1"; if (portName.Equals("1")) { index = "0"; } string line = "expect " + inoutPin + " " + inst.InstanceName + " " + inst.SliceName + " " + port.SlicePort + " " + portName + " " + index; OutputManager.WriteOutput(line); } } }
protected override void DoCommandAction() { FPGA.FPGATypes.AssertBackendType(FPGA.FPGATypes.BackendType.ISE, FPGA.FPGATypes.BackendType.Vivado); // map a library element port to // kind (internal, external, no vecotr Dictionary <string, string> signals = new Dictionary <string, string>(); // and to a signal name Dictionary <string, PortMapper.MappingKind> mappings = new Dictionary <string, PortMapper.MappingKind>(); Dictionary <string, List <int> > stepWidth = new Dictionary <string, List <int> >(); foreach (string triplet in PortMapping) { string[] atoms = triplet.Split(':'); if (atoms.Length < 2) { throw new ArgumentException("Unexpected format in PortMapping. See parameter description for an example"); } string libraryElementPortNameRegexp = atoms[0]; string connectedSignal = atoms[1]; // external is the default value PortMapper.MappingKind mapping = PortMapper.MappingKind.External; if (atoms.Length == 3) { switch (atoms[2]) { case "internal": { mapping = PortMapper.MappingKind.Internal; break; } case "external": { mapping = PortMapper.MappingKind.External; break; } case "no_vector": { mapping = PortMapper.MappingKind.NoVector; break; } default: { throw new ArgumentException("Unexpected value " + triplet + "in PortMapping. See parameter description for an example"); } } } signals[libraryElementPortNameRegexp] = connectedSignal; mappings[libraryElementPortNameRegexp] = mapping; stepWidth[libraryElementPortNameRegexp] = new List <int>(); if (atoms.Length == 4) { foreach (string intAsString in atoms[3].Split('-')) { stepWidth[libraryElementPortNameRegexp].Add(int.Parse(intAsString)); } } } if (LibraryElementFilter.Contains("LUT")) { } foreach (string libraryElementPortNameRegexp in signals.Keys) { // index with every signal // two use case: increment or stepwidth int index = StartIndex; int wraps = 0; foreach (LibElemInst inst in LibraryElementInstanceManager.Instance.GetAllInstantiations().Where(inst => Regex.IsMatch(inst.InstanceName, InstantiationFilter) && Regex.IsMatch(inst.LibraryElementName, LibraryElementFilter))) { LibraryElement libElement = Objects.Library.Instance.GetElement(inst.LibraryElementName); foreach (XDLPort port in libElement.Containter.Ports.Where(p => Regex.IsMatch(p.ExternalName, libraryElementPortNameRegexp)).OrderBy(p => p.ExternalName)) { if (port.ConstantValuePort) { inst.PortMapper.AddMapping(port.ExternalName, "0", PortMapper.MappingKind.External, index); } else { if (index >= stepWidth[libraryElementPortNameRegexp].Count && stepWidth[libraryElementPortNameRegexp].Count > 0) { wraps++; index = 0; } int nextIndex = stepWidth[libraryElementPortNameRegexp].Count == 0 ? index : stepWidth[libraryElementPortNameRegexp].Count * wraps + stepWidth[libraryElementPortNameRegexp][index]; inst.PortMapper.AddMapping( port.ExternalName, signals[libraryElementPortNameRegexp], mappings[libraryElementPortNameRegexp], nextIndex); index += StepWidth; } } } } }
public string GetSubsystemInstantiation() { StringBuilder buffer = new StringBuilder(); buffer.AppendLine("-- This file was automatically generated by GoAhead"); buffer.AppendLine(""); buffer.AppendLine("-- component_declaration"); buffer.AppendLine("component " + m_name + " is port ("); buffer.Append(Entity.ToString()); buffer.AppendLine("end component " + m_name + ";"); buffer.AppendLine(""); buffer.AppendLine("-- attribute_declaration"); buffer.AppendLine("attribute s : string;"); buffer.AppendLine("attribute keep : string;"); buffer.AppendLine("-- signal_declaration"); foreach (Tuple <string, int> s in Entity.GetSignals()) { PortMapper.MappingKind mapping = Entity.HasMapping(s.Item1) ? Entity.GetMapping(s.Item1) : PortMapper.MappingKind.External; switch (mapping) { case PortMapper.MappingKind.NoVector: buffer.AppendLine("signal " + s.Item1 + " : std_logic := '1';"); break; case PortMapper.MappingKind.Internal: case PortMapper.MappingKind.External: buffer.AppendLine("signal " + s.Item1 + " : std_logic_vector(" + (s.Item2 - 1) + " downto 0) := (others => '1');"); break; default: break; } } buffer.AppendLine("-- attribute_assignment"); foreach (Tuple <string, int> s in Entity.GetSignals()) { buffer.AppendLine("attribute s of " + s.Item1 + " : signal is \"true\";"); } foreach (Tuple <string, int> s in Entity.GetSignals()) { buffer.AppendLine("attribute keep of " + s.Item1 + " : signal is \"true\";"); } buffer.AppendLine(""); buffer.AppendLine("-- instantiation_code"); buffer.AppendLine("inst_" + m_name + " : " + m_name); buffer.AppendLine("port map ("); List <string> assignments = new List <string>(); foreach (Tuple <string, int> s in Entity.GetSignals()) { assignments.Add("\t" + s.Item1 + " => " + s.Item1 + ","); } if (assignments.Count > 0) { assignments[assignments.Count - 1] = Regex.Replace(assignments[assignments.Count - 1], ",", ""); } foreach (string a in assignments) { buffer.AppendLine(a); } buffer.AppendLine(");"); return(buffer.ToString()); }
private void IntergrateIntoContainer(Command callee) { m_instanceCode.AppendLine("-- instantiation of " + m_instantation.InstanceName); m_instanceCode.AppendLine(m_instantation.InstanceName + " : " + m_instantation.GetLibraryElement().PrimitiveName); if (!string.IsNullOrEmpty(m_libraryElement.VHDLGenericMap)) { m_instanceCode.AppendLine(m_libraryElement.VHDLGenericMap); } m_instanceCode.AppendLine("port map ("); List <string> mappings = new List <string>(); foreach (XDLPort port in ((XDLContainer)m_libraryElement.Containter).Ports) { if (!m_instantation.PortMapper.HasKindMapping(port.ExternalName)) { callee.OutputManager.WriteOutput("Warning: Could not find a signal mapping for port " + port.ExternalName + ". Misspelled mapping? Note that the mapping is case sensitive."); continue; } PortMapper mapper = m_instantation.PortMapper; PortMapper.MappingKind mappingKind = mapper.GetMapping(port.ExternalName); string rightHandSide = mapper.GetSignalName(port.ExternalName); // do not vectorize already indeced ports //bool vector = Regex.IsMatch(port.ExternalName, @"\d+$") && !Regex.IsMatch(rightHandSide, @"\(\d+\)$"); if (rightHandSide.Equals("0") || rightHandSide.Equals("1")) { mappings.Add("\t" + port.ExternalName + " => " + "'" + rightHandSide + "',"); } else if (rightHandSide.Equals("open")) { mappings.Add("\t" + port.ExternalName + " => open,"); } else if (!rightHandSide.Equals("open")) { VHDLSignalList signalList = null; switch (mappingKind) { case PortMapper.MappingKind.NoVector: case PortMapper.MappingKind.External: { // in case of entity signals add direction signalList = m_container.Entity; m_container.Entity.SetDirection(rightHandSide, port.Direction); break; } case PortMapper.MappingKind.Internal: { signalList = m_container.SignalDeclaration; break; } default: throw new ArgumentException("Found port mapped to " + mappingKind + ". This mapping is not supported. Use either public or external, see command AddPortMapping"); } if (!signalList.HasSignal(rightHandSide)) { if (m_instantation.PortMapper.HasKindMapping(port.ExternalName)) { signalList.Add(rightHandSide, 1, m_instantation.PortMapper.GetMapping(port.ExternalName)); } else { signalList.Add(rightHandSide, 1); } } switch (mappingKind) { case PortMapper.MappingKind.Internal: case PortMapper.MappingKind.External: { //int index = signalList.GetSignalWidth(rightHandSide) - 1; int index = mapper.GetIndex(port.ExternalName); mappings.Add("\t" + port.ExternalName + " => " + rightHandSide + "(" + index + "),"); if (!signalList.HasSignal(rightHandSide)) { signalList.Add(rightHandSide, -1); } if (signalList.GetSignalWidth(rightHandSide) <= index) { signalList.SetSignalWidth(rightHandSide, index + 1); } // store the index generated during VHDL generation for interface checks //this.m_instantation.GetPortMapper().SetIndex(port.ExternalName, index); break; } case PortMapper.MappingKind.NoVector: { mappings.Add("\t" + port.ExternalName + " => " + rightHandSide + ","); break; } default: throw new ArgumentException("Found port mapped to " + mappingKind + ". This mapping is not supported. Use either public or external, see command AddPortMapping"); } } } if (mappings.Count > 0) { mappings[mappings.Count - 1] = Regex.Replace(mappings[mappings.Count - 1], ",$", ""); } // update tool info //Tile t = FPGA.FPGA.Instance.GetTile(m_instantation.AnchorLocation); //Blackboard.Instance.ClearToolTipInfo(t); foreach (string str in mappings) { m_instanceCode.AppendLine(str); // update tool info if (!str.EndsWith(" => ,")) { string toolTip = str; toolTip = Regex.Replace(toolTip, @"^\s+", ""); toolTip = Regex.Replace(toolTip, ",", ""); toolTip += Environment.NewLine; //Blackboard.Instance.AddToolTipInfo(t, toolTip); } } m_instanceCode.AppendLine(");"); }