private void Inst_Dmfc1(MipsInstruction inst) { if (!CheckCop1Usable()) { CauseException = ExceptionCode.CopUnstable; return; } if (!CheckEvenOddAllowed(inst.Fs)) { CauseFPUException(FPUExceptionType.Unimplemented); return; } UInt64 value = 0; if (MipsState.CP0Regs.StatusReg.AdditionalFPR) { value = MipsState.Fpr.ReadFPRUnsigned(inst.Fs); } else { value = MipsState.Fpr.ReadFPR32Unsigned(inst.Fs + 1) << 32; value |= MipsState.Fpr.ReadFPR32Unsigned(inst.Fs); } MipsState.WriteGPRUnsigned(inst.Rt, value); }
private void Inst_Lhu(MipsInstruction inst) { try { Int64 address = ComputeAddress(inst); if ((address & 1) != 0) { CauseException = ExceptionCode.AddressErrorLoad; return; } if (!MipsState.Operating64BitMode) { MipsState.WriteGPR32Unsigned(inst.Rt, DataManipulator.LoadHalfwordUnsigned(address)); } else { MipsState.WriteGPRUnsigned(inst.Rt, DataManipulator.LoadHalfwordUnsigned(address)); } } catch (TLBException tlbe) { switch (tlbe.ExceptionType) { case TLBExceptionType.Invalid: CauseException = ExceptionCode.Invalid; break; case TLBExceptionType.Mod: CauseException = ExceptionCode.TlbMod; break; case TLBExceptionType.Refill: CauseException = ExceptionCode.TlbStore; break; default: break; } } }
private void Inst_Andi(MipsInstruction inst) { if (!MipsState.Operating64BitMode) { MipsState.WriteGPR32Unsigned(inst.Rt, MipsState.ReadGPR32Unsigned(inst.Rs) & (UInt32)inst.Immediate); } else { MipsState.WriteGPRUnsigned(inst.Rt, MipsState.ReadGPRUnsigned(inst.Rs) & (UInt64)inst.Immediate); } }
private void Inst_Dsrlv(MipsInstruction inst) { if (MipsState.Operating64BitMode) { MipsState.WriteGPRUnsigned(inst.Rd, MipsState.ReadGPRUnsigned(inst.Rt) >> (Int32)(MipsState.ReadGPR32Unsigned(inst.Rs) & 0x3FUL)); } else { CauseException = ExceptionCode.ReservedInstruction; } }
private void Inst_Dsrl32(MipsInstruction inst) { if (MipsState.Operating64BitMode) { MipsState.WriteGPRUnsigned(inst.Rd, MipsState.ReadGPRUnsigned(inst.Rt) >> (32 + inst.ShiftAmount)); } else { CauseException = ExceptionCode.ReservedInstruction; } }
private void Inst_Dmfc0(MipsInstruction inst) { if (MipsState.Operating64BitMode) { MipsState.WriteGPRUnsigned(inst.Rt, MipsState.CP0Regs[inst.Rd]); } else { CauseException = ExceptionCode.ReservedInstruction; } }
private void Inst_Xor(MipsInstruction inst) { if (!MipsState.Operating64BitMode) { MipsState.WriteGPR32Unsigned(inst.Rd, MipsState.ReadGPR32Unsigned(inst.Rs) ^ MipsState.ReadGPR32Unsigned(inst.Rt)); } else { MipsState.WriteGPRUnsigned(inst.Rd, MipsState.ReadGPRUnsigned(inst.Rs) ^ MipsState.ReadGPRUnsigned(inst.Rt)); } }
private void Inst_Srl(MipsInstruction inst) { UInt32 result = MipsState.ReadGPR32Unsigned(inst.Rt) >> inst.ShiftAmount; if (!MipsState.Operating64BitMode) { MipsState.WriteGPR32Unsigned(inst.Rd, result); } else { MipsState.WriteGPRUnsigned(inst.Rd, (UInt64)(Int64)(Int16)result); } }
private void Inst_Srvl(MipsInstruction inst) { UInt32 result = MipsState.ReadGPR32Unsigned(inst.Rt) >> MipsState.ReadGPR32Signed(inst.Rs) & 0x1F; if (!MipsState.Operating64BitMode) { MipsState.WriteGPR32Unsigned(inst.Rd, result); } else { MipsState.WriteGPRUnsigned(inst.Rd, (UInt32)(Int32)result); } }
private void Inst_Lui(MipsInstruction inst) { UInt32 word = ((UInt32)inst.Immediate) << 16; if (!MipsState.Operating64BitMode) { MipsState.WriteGPR32Unsigned(inst.Rt, word); } else { MipsState.WriteGPRUnsigned(inst.Rt, (UInt64)(Int64)(Int32)word); } }
private void Inst_Sltiu(MipsInstruction inst) { if (!MipsState.Operating64BitMode) { Boolean condition = MipsState.ReadGPR32Unsigned(inst.Rs) < ((UInt32)(Int32)(Int16)inst.Immediate); MipsState.WriteGPR32Unsigned(inst.Rt, condition ? 1U : 0U); } else { Boolean condition = MipsState.ReadGPRUnsigned(inst.Rs) < ((UInt64)(Int64)(Int16)inst.Immediate); MipsState.WriteGPRUnsigned(inst.Rt, condition ? 1UL : 0UL); } }
private void Inst_Dsubu(MipsInstruction inst) { if (MipsState.Operating64BitMode) { unchecked { MipsState.WriteGPRUnsigned(inst.Rd, MipsState.ReadGPRUnsigned(inst.Rs) - MipsState.ReadGPRUnsigned(inst.Rt)); } } else { CauseException = ExceptionCode.ReservedInstruction; } }
private void Inst_Daddiu(MipsInstruction inst) { if (!MipsState.Operating64BitMode) { CauseException = ExceptionCode.ReservedInstruction; } else { unchecked { MipsState.WriteGPRUnsigned(inst.Rd, MipsState.ReadGPRUnsigned(inst.Rs) + (UInt64)(Int64)(Int16)inst.Immediate); } } }
private void Inst_Ldr(MipsInstruction inst) { if (MipsState.Operating64BitMode) { /* Thanks to PJ64 Implementation */ Int64 address = ComputeAddress(inst); Int32 offset = (Int32)(address & 7); UInt64 value = DataManipulator.LoadDoublewordUnsigned(address & ~7); MipsState.WriteGPRUnsigned(inst.Rt, MipsState.ReadGPRUnsigned(inst.Rt) & LDRMask[offset]); MipsState.WriteGPRUnsigned(inst.Rt, MipsState.ReadGPRUnsigned(inst.Rt) + (value >> LDRShift[offset])); } else { CauseException = ExceptionCode.ReservedInstruction; } }
private void Inst_Addiu(MipsInstruction inst) { unchecked { if (!MipsState.Operating64BitMode) { MipsState.WriteGPR32Unsigned(inst.Rt, MipsState.ReadGPR32Unsigned(inst.Rs) + (UInt32)(Int32)(Int16)inst.Immediate); } else { if (MipsState.ReadGPRUnsigned(inst.Rs).IsSigned32()) { MipsState.WriteGPRUnsigned(inst.Rt, MipsState.ReadGPRUnsigned(inst.Rs) + (UInt64)(Int64)(Int16)inst.Immediate); } } } }
private void Inst_Mfc1(MipsInstruction inst) { if (!CheckCop1Usable()) { CauseException = ExceptionCode.CopUnstable; return; } if (!MipsState.Operating64BitMode) { MipsState.WriteGPR32Unsigned(inst.Rt, MipsState.Fpr.ReadFPR32Unsigned(inst.Fs)); } else { MipsState.WriteGPRUnsigned(inst.Rt, MipsState.Fpr.ReadFPR32Unsigned(inst.Fs)); } }
private void Inst_Addu(MipsInstruction inst) { unchecked { if (!MipsState.Operating64BitMode) { MipsState.WriteGPR32Unsigned(inst.Rd, MipsState.ReadGPR32Unsigned(inst.Rs) + MipsState.ReadGPR32Unsigned(inst.Rt)); } else { if (MipsState.ReadGPRUnsigned(inst.Rs).IsSigned32() && MipsState.ReadGPRUnsigned(inst.Rt).IsSigned32()) { MipsState.WriteGPRUnsigned(inst.Rd, MipsState.ReadGPRUnsigned(inst.Rs) + MipsState.ReadGPRUnsigned(inst.Rt)); } } } }
private void Inst_Cfc1(MipsInstruction inst) { if (!CheckCop1Usable()) { CauseException = ExceptionCode.CopUnstable; return; } if (inst.Rd == 0) { MipsState.WriteGPRUnsigned(inst.Rd, MipsState.FCR0); } if (inst.Rd == 31) { MipsState.WriteGPRUnsigned(inst.Rd, MipsState.FCR31.RegisterValue); } }
private void Inst_Lwu(MipsInstruction inst) { if (!MipsState.Operating64BitMode) { CauseException = ExceptionCode.ReservedInstruction; return; } Int64 address = ComputeAddress(inst); if ((address & 3) != 0) { CauseException = ExceptionCode.AddressErrorLoad; } else { MipsState.WriteGPRUnsigned(inst.Rt, DataManipulator.LoadWordUnsigned(address)); } }
private void Inst_Sllv(MipsInstruction inst) { Int32 shiftAmount = MipsState.ReadGPR32Signed(inst.Rs) & 0x1F; if (!MipsState.Operating64BitMode) { MipsState.WriteGPR32Unsigned(inst.Rd, MipsState.ReadGPR32Unsigned(inst.Rt) << shiftAmount); } else { UInt64 result = MipsState.ReadGPRUnsigned(inst.Rt) << shiftAmount; /* Truncate */ if (shiftAmount == 0) { MipsState.WriteGPRSigned(inst.Rd, (Int32)(UInt32)result); } else { MipsState.WriteGPRUnsigned(inst.Rd, result); } } }
private void Inst_Mfc0(MipsInstruction inst) { if (MipsState.CP0Regs.StatusReg.CopUsable0) { if (!MipsState.Operating64BitMode) { MipsState.WriteGPR32Unsigned(inst.Rt, (UInt32)MipsState.CP0Regs[inst.Rd]); /* Count register */ if (inst.Rt == 9) { MupenHelper.UpdateCount(); } } else { MipsState.WriteGPRUnsigned(inst.Rt, MipsState.CP0Regs[inst.Rd]); } } else { CauseException = ExceptionCode.CopUnstable; } }
private void Inst_Nor(MipsInstruction inst) { MipsState.WriteGPRUnsigned(inst.Rd, ~(MipsState.ReadGPRUnsigned(inst.Rs) | MipsState.ReadGPRUnsigned(inst.Rt))); }
private void Inst_Scd(MipsInstruction inst) { /* This is used in atomic operations, for now let it always pass */ MipsState.WriteGPRUnsigned(inst.Rt, 1); Inst_Sd(inst); }
private void Inst_Mflo(MipsInstruction inst) { MipsState.WriteGPRUnsigned(inst.Rd, MipsState.Lo); }