public DisassembledInstruction(Int64 address, String disasm, MipsInstruction instruction) { m_Address = address; m_Disasm = disasm; m_Instruction = instruction; Int32 hi = (Int32)(instruction.Instruction & 0xFF00) >> 16; Int32 lo = (Int32)(instruction.Instruction & 0x00FF); m_FullLine = String.Format("{0:X8} {1:X4} {2:X4} {3}", (UInt32)m_Address, hi, lo, m_Disasm); }
public static DisassemblyString Disassemble(MipsInstruction inst) { DisassemblyString disasm = new DisassemblyString(); if (inst.Instruction == 0) { disasm.Opcode = "nop"; disasm.Operands = ""; return(disasm); } String entity = s_OpTableMain[inst.Opcode]; String op = ""; String operands = ""; if (entity != null) { switch (entity) { case "_SPECIAL": { DecodeParts(inst, s_OpTableSpecial[inst.Function], ref op, ref operands); break; } case "_REGIMM": { DecodeParts(inst, s_OpTableRegImm[inst.Rt], ref op, ref operands); break; } case "_COP0": { switch (inst.Rs) { case 0x10: DecodeParts(inst, s_OpTableTlb[inst.Function], ref op, ref operands); break; default: DecodeParts(inst, s_OpTableCop0[inst.Rs], ref op, ref operands); break; } break; } case "_COP1": { switch (s_OpTableCop1[inst.Rs]) { case "_BC1": DecodeParts(inst, s_OpTableBC1[inst.Rt], ref op, ref operands); break; case "_FPU": DecodeParts(inst, s_OpTableFpu[inst.Function], ref op, ref operands); break; default: DecodeParts(inst, s_OpTableCop1[inst.Rs], ref op, ref operands); break; } break; } default: DecodeParts(inst, entity, ref op, ref operands); break; } disasm.Opcode = op; disasm.Operands = operands; return(disasm); } else { return(null); } }
public static Int64 JumpTarget(MipsInstruction inst) { return(Interpreter.JumpComputeTargetAddress(inst)); }
public static Int64 BranchTarget(MipsInstruction inst) { return(Interpreter.BranchComputeTargetAddress(inst)); }