public override string GetReport()
{
StringBuilder r = new StringBuilder();
r.Append(base.GetReport());
r.Append("Microarchitecture: ");
r.AppendLine(microarchitecture.ToString());
r.Append("Time Stamp Counter Multiplier: ");
r.AppendLine(timeStampCounterMultiplier.ToString(
CultureInfo.InvariantCulture));
r.AppendLine();
return(r.ToString());
}
public IntelCPU(int processorIndex, CPUID[][] cpuid, ISettings settings)
: base(processorIndex, cpuid, settings)
{
// set tjMax
float[] tjMax;
switch (family)
{
case 0x06:
{
switch (model)
{
case 0x0F: // Intel Core 2 (65nm)
microarchitecture = Microarchitecture.Core;
switch (stepping)
{
case 0x06: // B2
switch (coreCount)
{
case 2:
tjMax = Floats(80 + 10); break;
case 4:
tjMax = Floats(90 + 10); break;
default:
tjMax = Floats(85 + 10); break;
}
tjMax = Floats(80 + 10); break;
case 0x0B: // G0
tjMax = Floats(90 + 10); break;
case 0x0D: // M0
tjMax = Floats(85 + 10); break;
default:
tjMax = Floats(85 + 10); break;
}
break;
case 0x17: // Intel Core 2 (45nm)
tjMax = Floats(100); break;
case 0x1C: // Intel Atom (45nm)
microarchitecture = Microarchitecture.Atom;
switch (stepping)
{
case 0x02: // C0
tjMax = Floats(90); break;
case 0x0A: // A0, B0
tjMax = Floats(100); break;
default:
tjMax = Floats(90); break;
}
break;
case 0x1A: // Intel Core i7 LGA1366 (45nm)
case 0x1E: // Intel Core i5, i7 LGA1156 (45nm)
case 0x1F: // Intel Core i5, i7
case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm)
case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core
case 0x2E: // Intel Xeon Processor 7500 series (45nm)
case 0x2F: // Intel Xeon Processor (32nm)
technology = 32;
microarchitecture = Microarchitecture.Nehalem;
tjMax = GetTjMaxFromMSR();
break;
case 0x2A: // Intel Core i5, i7 2xxx LGA1155 (32nm)
microarchitecture = Microarchitecture.SandyBridge;
tjMax = GetTjMaxFromMSR();
break;
case 0x2D: // Next Generation Intel Xeon, i7 3xxx LGA2011 (32nm)
microarchitecture = Microarchitecture.SandyBridge;
tjMax = GetTjMaxFromMSR();
break;
case 0x3A: // Intel Core i5, i7 3xxx LGA1155 (22nm)
case 0x3E: // Intel Core i7 4xxx LGA2011 (22nm)
tjMax = GetTjMaxFromMSR();
break;
case 0x3C: // Intel Core i5, i7 4xxx LGA1150 (22nm)
microarchitecture = Microarchitecture.Haswell;
tjMax = GetTjMaxFromMSR();
break;
case 0x3F: // Intel Xeon E5-2600/1600 v3, Core i7-59xx
// LGA2011-v3, Haswell-E (22nm)
case 0x45: // Intel Core i5, i7 4xxxU (22nm)
case 0x46:
microarchitecture = Microarchitecture.Haswell;
tjMax = GetTjMaxFromMSR();
break;
case 0x3D: // Intel Core M-5xxx (14nm)
microarchitecture = Microarchitecture.Broadwell;
tjMax = GetTjMaxFromMSR();
break;
case 0x4F: // Intel Core M-5xxx (14nm)
microarchitecture = Microarchitecture.Broadwell;
tjMax = GetTjMaxFromMSR();
break;
case 0x36: // Intel Atom S1xxx, D2xxx, N2xxx (32nm)
technology = 32;
microarchitecture = Microarchitecture.Atom;
tjMax = GetTjMaxFromMSR();
break;
case 0x37: // Intel Atom E3xxx, Z3xxx (22nm)
case 0x4A:
case 0x4D: // Intel Atom C2xxx (22nm)
case 0x5A:
case 0x5D:
technology = 22;
microarchitecture = Microarchitecture.Silvermont;
tjMax = GetTjMaxFromMSR();
break;
default:
microarchitecture = Microarchitecture.Unknown;
tjMax = Floats(100);
break;
}
}
break;
case 0x0F:
{
switch (model)
{
case 0x00: // Pentium 4 (180nm)
case 0x01: // Pentium 4 (130nm)
case 0x02: // Pentium 4 (130nm)
case 0x03: // Pentium 4, Celeron D (90nm)
case 0x04: // Pentium 4, Pentium D, Celeron D (90nm)
case 0x06: // Pentium 4, Pentium D, Celeron D (65nm)
microarchitecture = Microarchitecture.NetBurst;
tjMax = Floats(100);
break;
default:
microarchitecture = Microarchitecture.Unknown;
tjMax = Floats(100);
break;
}
}
break;
default:
microarchitecture = Microarchitecture.Unknown;
tjMax = Floats(100);
break;
}
// set timeStampCounterMultiplier
switch (microarchitecture)
{
case Microarchitecture.NetBurst:
case Microarchitecture.Atom:
case Microarchitecture.Core:
{
}
break;
case Microarchitecture.Nehalem:
case Microarchitecture.SandyBridge:
case Microarchitecture.IvyBridge:
case Microarchitecture.Haswell:
case Microarchitecture.Broadwell:
case Microarchitecture.Silvermont:
{
}
break;
default:
timeStampCounterMultiplier = 0;
break;
}
// check if processor supports a digital thermal sensor at core level
if (cpuid[0][0].Data.GetLength(0) > 6 &&
(cpuid[0][0].Data[6, 0] & 1) != 0 &&
microarchitecture != Microarchitecture.Unknown)
{
coreTemperatures = new Sensor[coreCount];
for (int i = 0; i < coreTemperatures.Length; i++)
{
coreTemperatures[i] = new Sensor(CoreString(i), i,
SensorType.Temperature, this, new[] {
new ParameterDescription(
"TjMax [°C]", "TjMax temperature of the core sensor.\n" +
"Temperature = TjMax - TSlope * Value.", tjMax[i]),
new ParameterDescription("TSlope [°C]",
"Temperature slope of the digital thermal sensor.\n" +
"Temperature = TjMax - TSlope * Value.", 1)
}, settings);
ActivateSensor(coreTemperatures[i]);
}
}
else
{
coreTemperatures = new Sensor[0];
}
// check if processor supports a digital thermal sensor at package level
if (cpuid[0][0].Data.GetLength(0) > 6 &&
(cpuid[0][0].Data[6, 0] & 0x40) != 0 &&
microarchitecture != Microarchitecture.Unknown)
{
packageTemperature = new Sensor("CPU Package",
coreTemperatures.Length, SensorType.Temperature, this, new[] {
new ParameterDescription(
"TjMax [°C]", "TjMax temperature of the package sensor.\n" +
"Temperature = TjMax - TSlope * Value.", tjMax[0]),
new ParameterDescription("TSlope [°C]",
"Temperature slope of the digital thermal sensor.\n" +
"Temperature = TjMax - TSlope * Value.", 1)
}, settings);
ActivateSensor(packageTemperature);
}
busClock = new Sensor("Bus Speed", 0, SensorType.Clock, this, settings);
coreClocks = new Sensor[coreCount];
for (int i = 0; i < coreClocks.Length; i++)
{
coreClocks[i] =
new Sensor(CoreString(i), i + 1, SensorType.Clock, this, settings);
if (HasTimeStampCounter && microarchitecture != Microarchitecture.Unknown)
{
ActivateSensor(coreClocks[i]);
}
}
if (microarchitecture == Microarchitecture.SandyBridge ||
microarchitecture == Microarchitecture.IvyBridge ||
microarchitecture == Microarchitecture.Haswell ||
microarchitecture == Microarchitecture.Broadwell ||
microarchitecture == Microarchitecture.Silvermont)
{
powerSensors = new Sensor[energyStatusMSRs.Length];
lastEnergyTime = new DateTime[energyStatusMSRs.Length];
lastEnergyConsumed = new uint[energyStatusMSRs.Length];
}
var familyModel = (ushort)((family << 8) + model);
if (FamilyModel.X86FamilyModelSteppingTable.ContainsKey(familyModel))
{
codeName = FamilyModel.X86FamilyModelSteppingTable[familyModel].CodeName;
technology = FamilyModel.X86FamilyModelSteppingTable[familyModel].Technology;
}
else
{
codeName = microarchitecture.ToString();
}
Update();
}
public AMDCPU(int processorIndex, CPUID[][] cpuid, ISettings settings) : base(processorIndex, cpuid, settings)
{
this.microarchitecture = Microarchitecture.Unknown;
System.Console.WriteLine(this.family);
switch (this.family)
{
case 0xC:
this.microarchitecture = Microarchitecture.K10;
break;
case 0xE:
this.microarchitecture = Microarchitecture.Bobcat;
break;
case 0x10:
switch (this.model)
{
case 0x2:
this.microarchitecture = Microarchitecture.Jaguar;
break;
case 0x3:
this.microarchitecture = Microarchitecture.Puma;
break;
}
break;
case 0x12:
this.microarchitecture = Microarchitecture.Bobcat;
break;
case 0x15:
switch (this.model)
{
case 0x1:
this.microarchitecture = Microarchitecture.Bulldozer;
break;
case 0x2:
this.microarchitecture = Microarchitecture.Piledriver;
break;
case 0x3:
this.microarchitecture = Microarchitecture.Steamroller;
break;
case 0x4:
this.microarchitecture = Microarchitecture.Excavator;
break;
}
break;
}
var familyModel = (ushort)((family << 8) + model);
if (FamilyModel.X86FamilyModelSteppingTable.ContainsKey(familyModel))
{
codeName = FamilyModel.X86FamilyModelSteppingTable[familyModel].CodeName;
technology = FamilyModel.X86FamilyModelSteppingTable[familyModel].Technology;
}
else
{
codeName = microarchitecture.ToString();
}
}