0x313020524f525245; // ASCII = "10 RORRE" ~ "ERROR 01"
public static byte Memcached_Opcode(Memory_Operation op)
{
switch (op)
{
case Memory_Operation.GET:
return(GET_op);
case Memory_Operation.SET:
return(SET_op);
case Memory_Operation.DELETE:
return(DELETE_op);
}
return(GET_op); //FIXME fudge
}
// This procedure performs the basic control operation for the CAM.
protected static uint CAM_Control(Memory_Operation mode, ulong key)
{
uint tmp_addr = 0x00, addr = 0x00;
ulong tmp_key;
//tmp_addr=0x00;
bool busy = true;
// 1 cycle read latency, 16 cycles write latency
// mode=true , WRITE operation
//Kiwi.Pause();
// Poll until CAM is ready
while (cam_busy)
{
Kiwi.Pause();
}
//addr = mem_controller_cnt;
//tmp_key = key;
//if(mem_controller_cnt == (uint)(MEM_SIZE-1U)) mem_controller_cnt = 0;
switch (mode)
{ // WRITE operation - returns the address in which the key is stored
case Memory_Operation.SET: // 0x01
cam_din = key;
cam_wr_addr = (byte)mem_controller_cnt;
tmp_addr = (byte)mem_controller_cnt;
Kiwi.Pause();
cam_we = true;
Kiwi.Pause();
cam_we = false;
Kiwi.Pause();
break;
// READ operation - return the address if we have a match otherwhise MEM_SIZE
case Memory_Operation.GET: // 0x00
cam_cmp_din = key;
Kiwi.Pause();
cam_cmp_din = key;
Kiwi.Pause();
tmp_addr = (cam_match) ? (uint)cam_match_addr : (uint)MEM_SIZE;
break;
// DELETE operation - return the address if we have a match otherwhise MEM_SIZE
case Memory_Operation.DELETE: // 0x04
cam_cmp_din = key;
Kiwi.Pause();
cam_cmp_din = key;
Kiwi.Pause();
if (cam_match)
{
tmp_addr = (uint)cam_match_addr;
}
else
{
tmp_addr = (uint)MEM_SIZE;
}
Kiwi.Pause();
if (cam_match)
{
Kiwi.Pause();
cam_din = (ulong)0x00;
cam_wr_addr = (byte)tmp_addr;
Kiwi.Pause();
cam_we = true;
Kiwi.Pause();
cam_we = false;
Kiwi.Pause();
}
break;
default:
break;
}
if (mem_controller_cnt == (uint)(MEM_SIZE - 1U))
{
mem_controller_cnt = 0;
}
else
{
mem_controller_cnt += 1U;
}
return(tmp_addr);
}
