/// <summary>
/// Processor Construction Function
/// </summary>
/// <param name="insp_"> Shared Instruction Partitioner </param>
/// <param name="pid_"> Processor ID</param>
public PIMProc(ref InsPartition insp_, int pid_)
{
pid = pid_;
ins_p = insp_;
L1Cache = new Cache(true);
// Shared_Cache = new Cache(config, true);
ins_w = new InstructionWindow(Config.ins_w_size, pid);
IPC = PIMConfigs.IPC;
if (PIMConfigs.use_l1_cache)
{
cache_req_queue = new Queue <ProcRequest>();
}
MSHR = new List <ProcRequest>(Config.mshr_size);
cal_restrict = new Counter(Config.IPC, Config.IPC);
mem_restrict = new Counter(1, 1);
alu = new ALU();
tlb = new PageConverter();
if (PIMConfigs.writeback)
{
writeback_req = new List <ProcRequest>();
}
//init callback
read_callback = new ReadCallBack(handle_read_callback);
write_callback = new WriteCallBack(handle_write_callback);
}
public PIM(ref InsPartition ins_p_)
{
if (Config.DEBUG_PIM)
{
DEBUG.WriteLine("PIM Module Initialed.");
}
ins_p = ins_p_;
unit = new List <ComputationalUnit>();
if (PIMConfigs.unit_type == PIM_Unit_Type.Processors)
{
if (Config.DEBUG_PIM)
{
DEBUG.WriteLine("PIM Unit Type : Processors.");
}
for (int i = 0; i < PIMConfigs.N; i++)
{
var p = new PIMProc(ref ins_p, i);
unit.Add(p);
}
}
else
{
if (Config.DEBUG_PIM)
{
DEBUG.WriteLine("PIM Unit Type : Pipeline.");
}
//pipeline mode
// When PIMSim runs into pipeline mode, input should always be a Function.
for (int i = 0; i < PIMConfigs.CU_Name.Count; i++)
{
if (PIMConfigs.CU_Name[i] == "Customied")
{
//add your code here
}
else
{
if (PIMConfigs.CU_Name[i] == "Adder")
{
unit.Add(new Adder(i, ref ins_p) as ComputationalUnit);
return;
}
else
{
if (PIMConfigs.CU_Name[i] == "Adder_Conventional")
{
unit.Add(new Adder_Conventional(i, ref ins_p) as ComputationalUnit);
return;
}
else
{
DEBUG.Error("No PIM Unit templates.");
Environment.Exit(2);
}
}
}
}
}
}
public Adder_Conventional(int id_, ref InsPartition insp_)
{
this.id = id_;
input_count = 2;
output_count = 1;
isp = insp_;
//********************************************************
//** **
//** Stage 1-1: Load Data **
//** **
//********************************************************
var item_stage1 = new PIMStage_LoadData(this, 0);
pipeline[0] = (item_stage1 as Stage);
item_stage1 = null;
//********************************************************
//** **
//** Stage 1-2: Load data **
//** **
//********************************************************
var item_stage2 = new PIMStage_LoadData(this, 1);
pipeline[1] = item_stage2 as Stage;
item_stage2 = null;
//********************************************************
//** **
//** Stage 3: Calculation **
//** **
//********************************************************
var item_stage3 = new PIMStage_Computation(this, 2, latency_op);
item_stage3.set_link(ref pipeline[0]);
item_stage3.set_link(ref pipeline[1]);
pipeline[2] = item_stage3 as Stage;
//********************************************************
//** **
//** Stage 4: Write results back **
//** **
//********************************************************
var item_stage4 = new PIMStage_Store(this, 3);
item_stage4.set_link(ref pipeline[2]);
pipeline[3] = item_stage4 as Stage;
//init callback
read_callback = new ReadCallBack(handle_read_callback);
write_callback = new WriteCallBack(handle_write_callback);
}
/// <summary>
/// Processor Construction Function
/// </summary>
/// <param name="insp_"> Shared Instruction Partitioner </param>
/// <param name="pid_"> Processor ID</param>
public Proc(ref InsPartition insp_, int pid_)
{
//passing parameters
pid = pid_;
ins_p = insp_;
IPC = Config.IPC;
//init private cache
L1Cache = new Cache(false);
//init instruction window
ins_w = new InstructionWindow(Config.ins_w_size, pid);
//queue init
if (Config.use_cache)
{
cache_req_queue = new Queue <ProcRequest>();
}
MSHR = new List <ProcRequest>(Config.mshr_size);
if (Config.writeback)
{
writeback_req = new List <ProcRequest>();
}
//restrict
cal_restrict = new Counter(Config.IPC, Config.IPC);
mem_restrict = new Counter(1, 1);
//alu
alu = new ALU();
//init callback
read_callback = new ReadCallBack(handle_read_callback);
write_callback = new WriteCallBack(handle_write_callback);
ins_port = new InspCPUSlavePort("CPU Insrtuction Cache", PortManager.Allocate());
ins_port.owner = this;
}
public PIMSimulator(string[] args)
{
initAllconfigs(args);
trace = new TraceFetcher();
ins_p = new InsPartition();
pg = new PageConverter();
if (Config.shared_cache)
{
shared_cache = new Shared_Cache();
}
proc = new List <Proc>();
for (int i = 0; i < Config.N; i++)
{
Proc to_add = new Proc(ref ins_p, i);
if (Config.shared_cache)
{
to_add.attach_shared_cache(ref shared_cache);
}
to_add.attach_tlb(ref pg);
proc.Add(to_add);
}
int count = 0;
foreach (var item in Config.memory)
{
if (item.Key.Equals("HMC"))
{
var tp = new HMCMem(count++) as MemObject;
MemorySelector.add(item.Value, ref tp);
}
else
{
if (item.Key.Equals("DRAM") || item.Key.Equals("PCM"))
{
var tp = new DDRMem(count++) as MemObject;
MemorySelector.add(item.Value, ref tp);
}
else
{
//error
DEBUG.Error("Unknown Memory Type.");
Environment.Exit(3);
}
}
}
Mctrl.init_queue();
PIMMctrl.init_queue();
pim = new PIM.PIM(ref ins_p);
Coherence.init();
Coherence.linkproc(proc);
GlobalTimer.InitClock();
BuildTopology();
}
