public override void visit(Port obj) { if (obj.Parent.Impl is Tonka.TestComponent) { return; } if (CodeGenerator.polyComponentClasses .Contains((obj.Parent.Impl as Tonka.Component).Attributes.Classifications)) { return; } Logger.WriteDebug("CyPhySchematicVisitor::visit({0}, dest connections: {1})", obj.Name, obj.DstConnections.Count); if (PortNetMap.ContainsKey(obj))// port already mapped to a net object - no need to visit further { return; } if (obj.DstConnections.Count <= 0 && obj.SrcConnections.Count <= 0) // no source and dest connections - skip this port { return; } var net_obj = new Eagle.net(); net_obj.name = string.Format("N${0}", netCount++); visit(obj, net_obj); schematic_obj.sheets.sheet.FirstOrDefault().nets.net.Add(net_obj); // relying that a sheet has been created already }
private void visit(Port obj, Eagle.net net_obj) { if (obj.Parent.Impl is Tonka.TestComponent) { } else if (CodeGenerator.polyComponentClasses .Contains((obj.Parent.Impl as Tonka.Component).Attributes.Classifications)) { // remember this 'pcb' net for later processing in generating layout if (!CodeGenerator.polyNetMap.ContainsKey(obj)) { CodeGenerator.polyNetMap.Add(obj, net_obj); } } else { // create a segment for this object var segment_obj = new Eagle.segment(); CreateWireSegment(obj, segment_obj); // simple routing CreatePinRef(obj, segment_obj); // destination pin net_obj.segment.Add(segment_obj); } PortNetMap[obj] = net_obj; // add to map var allPorts = (from conn in obj.DstConnections select conn.DstPort).Union (from conn in obj.SrcConnections select conn.SrcPort); foreach (var port in allPorts) // visit sources { if (!PortNetMap.ContainsKey(port)) { this.visit(port, net_obj); } } }