public NetComponents(
ComponentChipDefinition componentChip,
List <Component> components,
Dictionary <StdLogic, Net> netMap,
DeclaredObjectContainer design,
Dictionary <StdLogic, Net> representingNet)
{
if (componentChip.componentCount < components.Count)
{
throw new Exception();
}
this.chip = componentChip;
this.id = ++NetComponents.count;
if (components.Count() == 1)
{
this.componentName = components[0].name;
}
for (int i = 0; i < components.Count; ++i)
{
foreach (var portPair in components[i].portMap)
{
var chipSignal = componentChip.portNameMappings[i][portPair.Key];
if (!(portPair.Value is StdLogic))
{
throw new CompilerException(
string.Format(@"Port signal ""{0}"" of chip ""{1}"" must be STD_LOGIC",
chipSignal.name, componentChip.chipName));
}
var netSignal = netMap[(StdLogic)portPair.Value];
if (!chipSignal.attribute.ContainsKey("pin_assign"))
{
throw new CompilerException(
string.Format(@"Port signal ""{0}"" of chip ""{1}"" does not have attribute ""pin_assignment""",
chipSignal.name, componentChip.chipName));
}
netSignal.adjacentNodes.Add(new Node(this, (int)chipSignal.attribute["pin_assign"]));
}
}
ProcesConstAssign(this, design, representingNet);
}
// チップのconst_assignを処理
void ProcesConstAssign(
NetComponents libParts,
DeclaredObjectContainer design,
Dictionary <StdLogic, Net> representingNet)
{
foreach (var constAssign in chip.constAssignMappings)
{
Net assignedNet;
if (constAssign.Value.baseName.ToLower() == "open")
{
var tempSignal = new StdLogic(design.signalNameGenerator.getSignalName());
assignedNet = representingNet[tempSignal] = new Net(".temp");
}
else
{
var assignedSignalName = constAssign.Value;
if (!design.signalTable.ContainsKey(assignedSignalName.baseName))
{
throw new CompilerException(
string.Format(@"Signal ""{0}"", which is specified in component ""{1}"" is not defined in the design file",
assignedSignalName.baseName, chip.chipName));
}
var assignedSignal = design.signalTable[assignedSignalName];
if (!(assignedSignal is StdLogic))
{
throw new CompilerException(
string.Format(@"Signal ""{0}"", which is specified in component ""{1}"" is not std_logic",
assignedSignalName.baseName, chip.chipName));
}
assignedNet = representingNet[(StdLogic)assignedSignal];
}
if (!constAssign.Key.attribute.ContainsKey("pin_assign"))
{
throw new CompilerException(
string.Format(@"Port signal ""{0}"" of chip ""{1}"" does not have attribute ""pin_assignment""",
constAssign.Key.name, chip.chipName));
}
int portPin = (int)constAssign.Key.attribute["pin_assign"];
assignedNet.adjacentNodes.Add(new Node(libParts, portPin));
}
}
public ComponentDeclarationEvaluator(DeclaredObjectContainer utility) : base(utility)
{
}
public ArchitectureDeclarativePartEvaluator(DeclaredObjectContainer utility) : base(utility)
{
}
public PrimaryEvaluator(DeclaredObjectContainer utility) : base(utility)
{
}
public EntityDeclarationEvaluator(DeclaredObjectContainer utility) : base(utility)
{
}
public NodeEvaluator(DeclaredObjectContainer utility = null)
{
this.declaredObjects = utility == null ? new DeclaredObjectContainer() : utility;
}
public FactorEvaluator(DeclaredObjectContainer utility) : base(utility)
{
}
public ComponentInstatiationStatementEvaluator(DeclaredObjectContainer utility) : base(utility)
{
}
public AttributeSpecificationEvaluator(DeclaredObjectContainer utility) : base(utility)
{
}
public ExpressionEvaluator(DeclaredObjectContainer utility) : base(utility)
{
}
public IdentifierListEvaluator(DeclaredObjectContainer utility) : base(utility)
{
}
public NetComponents(
GateChipDefinition gateChip,
List <LogicGate> gates,
Dictionary <StdLogic, Net> netMap,
DeclaredObjectContainer design,
Dictionary <StdLogic, Net> representingNet)
{
if (gateChip.gateCount < gates.Count)
{
throw new Exception();
}
this.chip = gateChip;
this.id = ++NetComponents.count;
for (int i = 0; i < gates.Count; ++i)
{
for (int j = 0; j < gates[i].inputSignals.Count; ++j)
{
var netInputSignal = netMap[(StdLogic)gates[i].inputSignals[j]];
var chipInputSignal = gateChip.portNameMappings[i][new StdLogic(new SignalName(".in" + j))];
if (!chipInputSignal.attribute.ContainsKey("pin_assign"))
{
throw new CompilerException(
string.Format(@"Port signal ""{0}"" of chip ""{1}"" does not have attribute ""pin_assignment""",
chipInputSignal.name, gateChip.chipName));
}
netInputSignal.adjacentNodes.Add(new Node(this, (int)chipInputSignal.attribute["pin_assign"]));
}
for (int j = gates[i].inputSignals.Count; j < gateChip.gateWidth; ++j)
{
var chipInputSignal = gateChip.portNameMappings[i][new StdLogic(new SignalName(".in" + j))];
if (!chipInputSignal.attribute.ContainsKey("pin_assign"))
{
throw new CompilerException(
string.Format(@"Port signal ""{0}"" of chip ""{1}"" does not have attribute ""pin_assignment""",
chipInputSignal.name, gateChip.chipName));
}
// ゲートの余った入力
if (gateChip.defaultHigh)
{
if (!design.signalTable.ContainsKey("VCC") || !(design.signalTable["VCC"] is StdLogic))
{
throw new CompilerException(
string.Format(@"Signal ""{0}"" was not found in design", "VCC"));
}
var vccSignal = (StdLogic)design.signalTable["VCC"];
netMap[vccSignal].adjacentNodes.Add(new Node(this, (int)chipInputSignal.attribute["pin_assign"]));
}
else
{
if (!design.signalTable.ContainsKey("GND") || !(design.signalTable["GND"] is StdLogic))
{
throw new CompilerException(
string.Format(@"Signal ""{0}"" was not found in design", "GND"));
}
var groundSignal = (StdLogic)design.signalTable["GND"];
netMap[groundSignal].adjacentNodes.Add(new Node(this, (int)chipInputSignal.attribute["pin_assign"]));
}
}
var netOutputSignal = netMap[(StdLogic)gates[i].outputSignal];
var chipOutputSignal = gateChip.portNameMappings[i][new StdLogic(new SignalName(".out"))];
if (!chipOutputSignal.attribute.ContainsKey("pin_assign"))
{
throw new CompilerException(
string.Format(@"Port signal ""{0}"" of chip ""{1}"" does not have attribute ""pin_assignment""",
chipOutputSignal.name, gateChip.chipName));
}
netOutputSignal.adjacentNodes.Add(new Node(this, (int)chipOutputSignal.attribute["pin_assign"]));
}
ProcesConstAssign(this, design, representingNet);
}
public void Compile(DeclaredObjectContainer design, List <IChipDefinition> chips)
{
this.representingNet = new Dictionary <StdLogic, Net>();
this.resComponentCount = new Dictionary <IChipDefinition, int>();
foreach (ISignal signal in design.signalTable.Values)
{
if (signal is StdLogic)
{
this.representingNet[(StdLogic)signal] = new Net(signal.name.ToString());
}
else if (signal is StdLogicVector)
{
var vector = (StdLogicVector)signal;
for (int i = 0; i < vector.size; ++i)
{
var stdLogic = vector.GetLogic(vector.stRange + i);
this.representingNet[stdLogic] = new Net(stdLogic.name.ToString());
}
}
}
// 代入されたネットの統一
foreach (var assignment in design.assignments)
{
if (assignment.Key is StdLogic && assignment.Value is StdLogic)
{
this.representingNet[(StdLogic)assignment.Key] = this.representingNet[(StdLogic)assignment.Value];
}
else if (assignment.Key is StdLogicVector && assignment.Value is StdLogicVector)
{
var leftVector = (StdLogicVector)assignment.Key;
var rightVector = (StdLogicVector)assignment.Value;
if (leftVector.size != rightVector.size)
{
throw new Exception();
}
for (int i = 0; i < leftVector.size; ++i)
{
this.representingNet[leftVector.GetLogic(leftVector.stRange + i)] =
this.representingNet[rightVector.GetLogic(rightVector.stRange + i)];
}
}
else
{
throw new Exception();
}
}
// 使用されている全てのチップが宣言されているか
var componentChips = new Dictionary <ComponentPrototype, ComponentChipDefinition>();
var gateChips = new Dictionary <LogicGate.GateType, SortedDictionary <int, GateChipDefinition> >();
foreach (var chipDeclaration in chips)
{
if (chipDeclaration is ComponentChipDefinition)
{
componentChips[((ComponentChipDefinition)chipDeclaration).componentPrototype] = (ComponentChipDefinition)chipDeclaration;
}
else if (chipDeclaration is GateChipDefinition)
{
var gateChipDefinition = (GateChipDefinition)chipDeclaration;
if (!gateChips.ContainsKey(gateChipDefinition.gateType))
{
gateChips[gateChipDefinition.gateType] = new SortedDictionary <int, GateChipDefinition>();
}
gateChips[gateChipDefinition.gateType][gateChipDefinition.gateWidth] = gateChipDefinition;
}
}
foreach (var component in design.components)
{
if (!componentChips.ContainsKey(component.prototype))
{
throw new CompilerException(
string.Format(@"No component chip definition was found for component ""{0}""", component.prototype.name));
}
}
foreach (var gate in design.logicGates)
{
if (!gateChips.ContainsKey(gate.gateType))
{
throw new CompilerException(
string.Format(@"No gate chip definition was found for gate ""{0}""", gate.gateType));
}
}
// 回路パーツに変換
this.netComponents = new List <NetComponents>();
var componentQueue = new Dictionary <ComponentPrototype, List <Component> >();
var gateQueue = new Dictionary <LogicGate.GateType, List <LogicGate> >();
foreach (var component in design.components)
{
if (!componentQueue.ContainsKey(component.prototype))
{
componentQueue[component.prototype] = new List <Component>();
}
componentQueue[component.prototype].Add(component);
}
foreach (var gate in design.logicGates)
{
if (!gateQueue.ContainsKey(gate.gateType))
{
gateQueue[gate.gateType] = new List <LogicGate>();
}
gateQueue[gate.gateType].Add(gate);
}
// GNDを取得
if (!design.signalTable.ContainsKey("GND") || !(design.signalTable["GND"] is StdLogic))
{
throw new CompilerException(
string.Format(@"Signal ""{0}"" was not found in design", "GND"));
}
var groundSignal = (StdLogic)design.signalTable["GND"];
// コンポーネントのチップを作成
foreach (var componentPrototype in componentQueue.Keys)
{
// コンポネントの名前で降順ソート
componentQueue[componentPrototype].Sort((x, y) =>
(new ComponentNameComparer()).Compare(y.name, x.name));
while (componentQueue[componentPrototype].Count > 0)
{
int dequeueCount = Math.Min(componentQueue[componentPrototype].Count, componentChips[componentPrototype].componentCount);
var components = new List <Component>();
for (int i = 0; i < dequeueCount; ++i)
{
components.Add(componentQueue[componentPrototype].Last());
componentQueue[componentPrototype].RemoveAt(componentQueue[componentPrototype].Count - 1);
}
this.resComponentCount[componentChips[componentPrototype]] = componentChips[componentPrototype].componentCount - dequeueCount;
// 余ったコンポネントの入力ポートをGNDに固定，出力ポートに仮の信号を接続
for (int i = dequeueCount; i < componentChips[componentPrototype].componentCount; ++i)
{
var portMap = new Dictionary <ISignal, ISignal>();
foreach (var portSignal in componentPrototype.signals)
{
if (portSignal.Value.mode == SignalMode.IN)
{
portMap[portSignal.Value] = groundSignal;
}
else if (portSignal.Value.mode == SignalMode.OUT || portSignal.Value.mode == SignalMode.INOUT)
{
var tempSignal = new StdLogic(design.signalNameGenerator.getSignalName());
this.representingNet[tempSignal] = new Net(".temp");
portMap[portSignal.Value] = tempSignal;
}
}
components.Add(new Component("dummy", componentPrototype, portMap));
}
var parts = new NetComponents(componentChips[componentPrototype], components, this.representingNet, design, this.representingNet);
this.netComponents.Add(parts);
}
}
// ゲートのチップを作成
foreach (var gateType in gateQueue.Keys)
{
int gateWidth = 0;
var gatePool = new List <LogicGate>();
gateQueue[gateType].Sort((x, y) => y.inputSignals.Count - x.inputSignals.Count);
foreach (var gate in gateQueue[gateType])
{
if (gatePool.Count == 0)
{
var gateWidthCandidate = gateChips[gateType].Keys.Where(x => x >= gate.inputSignals.Count);
if (gateWidthCandidate.Count() == 0)
{
throw new CompilerException(
string.Format(@"Gate {0}{1} is not defined", gateType, gate.inputSignals.Count));
}
gateWidth = gateWidthCandidate.First();
}
gatePool.Add(gate);
if (gatePool.Count == gateChips[gateType][gateWidth].gateCount)
{
this.resComponentCount[gateChips[gateType][gateWidth]] = 0;
var parts = new NetComponents(gateChips[gateType][gateWidth], gatePool, this.representingNet, design, this.representingNet);
this.netComponents.Add(parts);
gatePool.Clear();
}
}
if (gatePool.Count > 0)
{
// 余ったゲートの入力をGNDに固定，出力に仮の信号を接続したゲートを追加
var groundSignals = new List <ISignal>();
for (int i = 0; i < gateWidth; ++i)
{
groundSignals.Add(groundSignal);
}
this.resComponentCount[gateChips[gateType][gateWidth]] = gateChips[gateType][gateWidth].gateCount - gatePool.Count;
for (int i = gatePool.Count; i < gateChips[gateType][gateWidth].gateCount; ++i)
{
var tempSignal = new StdLogic(design.signalNameGenerator.getSignalName());
this.representingNet[tempSignal] = new Net(".temp");
gatePool.Add(new LogicGate(gateType, groundSignals, tempSignal));
}
var parts = new NetComponents(gateChips[gateType][gateWidth], gatePool, this.representingNet, design, this.representingNet);
this.netComponents.Add(parts);
}
}
}
public ConcurrentSignalAssignmentStatementEvaluator(DeclaredObjectContainer utility) : base(utility)
{
}
public RangeConstraintEvaluator(DeclaredObjectContainer utility) : base(utility)
{
}
