Exemple #1
0
 public ActionResult MachineDetails(int Id)
 {
     ViewBag.LoadManchineTypes = LoadManchineTypes();
     ViewBag.LoadManufacturers = LoadManufacturers();
     Core.Machine machine = _IMachineRepository.FindById(Id);
     return(View(machine));
 }
Exemple #2
0
        public ActionResult EditMachine(int Id)
        {
            ViewBag.Machine = "Update Machine";
            Core.Machine machine      = _IMachineRepository.FindById(Id);
            MachineModel machineModel = new MachineModel();

            machineModel.MachineId    = machine.MachineId;
            machineModel.MachineType  = machine.MachineType;
            machineModel.Manufacturer = machine.Manufacturer;
            machineModel.Price        = machine.Price;
            machineModel.Model        = machine.Model;
            machineModel.Year         = machine.Year;
            machineModel.RPM          = machine.RPM;
            machineModel.Table        = machine.TableName;
            machineModel.Description  = machine.Description;
            machineModel.Sold         = machine.Sold;
            machineModel.MachinePic1  = machine.MachinePic1;
            machineModel.MachinePic2  = machine.MachinePic2;
            machineModel.MachinePic3  = machine.MachinePic3;
            machineModel.MachinePic4  = machine.MachinePic4;

            machineModel.MachineTypes  = LoadManchineTypes();
            machineModel.Manufacturers = LoadManufacturers();

            return(View("AddNewMachine", machineModel));
        }
        public PicoRV32(Core.Machine machine, string cpuType, bool latchedIrqs = true, uint hartId = 0, uint resetVectorAddress = 0x10) : base(null, cpuType, machine, hartId, PrivilegeArchitecture.Priv1_09, Endianess.LittleEndian)
        {
            this.latchedIrqs = latchedIrqs;

            // the frequency value is picked at random and not tested
            internalTimer = new LimitTimer(machine.ClockSource, 1000000, this, nameof(internalTimer), workMode: WorkMode.OneShot, eventEnabled: true);
            internalTimer.LimitReached += () =>
            {
                lock (irqLock)
                {
                    pendingInterrupts |= (1u << TimerInterruptSource);
                    TlibSetReturnRequest();
                }
            };

            qRegisters = new uint[NumberOfQRegisters];

            // this will enable handling interrupts locally
            TlibSetReturnOnException(1);

            this.resetVectorAddress = resetVectorAddress;

            InstallCustomInstruction(pattern: "0000000-----000ss---ddddd0001011", handler: HandleGetqInstruction);
            InstallCustomInstruction(pattern: "0000001-----sssss---000dd0001011", handler: HandleSetqInstruction);
            InstallCustomInstruction(pattern: "0000010-----00000---000000001011", handler: HandleRetirqInstruction);
            InstallCustomInstruction(pattern: "0000011-----sssss---ddddd0001011", handler: HandleMaskirqInstruction);
            InstallCustomInstruction(pattern: "0000100-----00000---ddddd0001011", handler: HandleWaitirqInstruction);
            InstallCustomInstruction(pattern: "0000101-----sssss---ddddd0001011", handler: HandleTimerInstruction);

            Reset();
        }
        public VexRiscv(Core.Machine machine, uint hartId = 0, IRiscVTimeProvider timeProvider = null, PrivilegeArchitecture privilegeArchitecture = PrivilegeArchitecture.Priv1_09, string cpuType = "rv32im", bool builtInIrqController = true) : base(timeProvider, cpuType, machine, hartId, privilegeArchitecture, Endianess.LittleEndian)
        {
            this.builtInIrqController = builtInIrqController;
            if (builtInIrqController)
            {
                RegisterCustomCSRs();
            }

            RegisterCustomInstructions();
        }
Exemple #5
0
        public ActionResult EditMachine(MachineModel machineModel)
        {
            Core.Machine Machine = _IMachineRepository.FindById(machineModel.ID);

            if (machineModel.files.Count() == 4)
            {
                //delete images from image MachineImages folder
                DirectoryInfo hdDirectoryInWhichToSearch = new DirectoryInfo(Server.MapPath("~/MachineImages"));
                FileInfo[]    filesInDir = hdDirectoryInWhichToSearch.GetFiles("*" + Machine.MachineId + "*.*");

                foreach (FileInfo foundFile in filesInDir)
                {
                    System.IO.File.Delete(foundFile.FullName);
                }
            }
            //add new machines
            //saving images
            if (machineModel.files.Count() == 4)
            {
                foreach (var file in machineModel.files)
                {
                    if (file != null && file.ContentLength > 0)
                    {
                        string filePath = Path.Combine(Server.MapPath("~/MachineImages"), machineModel.MachineId + "-" + file.FileName);

                        file.SaveAs(filePath);
                    }
                }
            }

            Machine.MachineId    = machineModel.MachineId;
            Machine.MachineType  = machineModel.MachineType;
            Machine.Manufacturer = machineModel.Manufacturer;
            Machine.Price        = machineModel.Price;
            Machine.Model        = machineModel.Model;
            Machine.Year         = machineModel.Year;
            Machine.RPM          = machineModel.RPM;
            Machine.TableName    = machineModel.Table;
            Machine.Description  = machineModel.Description;
            if (machineModel.files.Count() == 4)
            {
                Machine.MachinePic1 = machineModel.MachineId + "-" + machineModel.files[0].FileName;
                Machine.MachinePic2 = machineModel.MachineId + "-" + machineModel.files[1].FileName;
                Machine.MachinePic3 = machineModel.MachineId + "-" + machineModel.files[2].FileName;
                Machine.MachinePic4 = machineModel.MachineId + "-" + machineModel.files[3].FileName;
            }
            Machine.ModifiedDate = DateTime.Now;
            Machine.Sold         = machineModel.Sold;

            _IMachineRepository.Edit(Machine);
            return(RedirectToAction("ListOfMachines"));
        }
        public VexRiscv(Core.Machine machine, uint hartId = 0, IRiscVTimeProvider timeProvider = null, PrivilegeArchitecture privilegeArchitecture = PrivilegeArchitecture.Priv1_09, string cpuType = "rv32im") : base(timeProvider, cpuType, machine, hartId, privilegeArchitecture, Endianess.LittleEndian)
        {
            // validate only privilege level when accessing CSRs
            // do not validate rw bit as VexRiscv custom CSRs do not follow the standard
            CSRValidation = CSRValidationLevel.PrivilegeLevel;

            RegisterCSR((ulong)CSRs.MachineIrqMask, () => (ulong)machineInterrupts.Mask, value =>
            {
                lock (locker)
                {
                    machineInterrupts.Mask = (uint)value;
                    this.Log(LogLevel.Noisy, "Machine IRQ mask set to 0x{0:X}", machineInterrupts.Mask);
                    Update();
                }
            });
            RegisterCSR((ulong)CSRs.MachineIrqPending, () => (ulong)machineInterrupts.Pending, value =>
            {
                lock (locker)
                {
                    machineInterrupts.Pending = (uint)value;
                    this.Log(LogLevel.Noisy, "Machine IRQ pending set to 0x{0:X}", machineInterrupts.Pending);
                    Update();
                }
            });
            RegisterCSR((ulong)CSRs.SupervisorIrqMask, () => (ulong)supervisorInterrupts.Mask, value =>
            {
                lock (locker)
                {
                    supervisorInterrupts.Mask = (uint)value;
                    this.Log(LogLevel.Noisy, "Supervisor IRQ mask set to 0x{0:X}", supervisorInterrupts.Mask);
                    Update();
                }
            });
            RegisterCSR((ulong)CSRs.SupervisorIrqPending, () => (ulong)supervisorInterrupts.Pending, value =>
            {
                lock (locker)
                {
                    supervisorInterrupts.Pending = (uint)value;
                    this.Log(LogLevel.Noisy, "Supervisor IRQ pending set to 0x{0:X}", supervisorInterrupts.Pending);
                    Update();
                }
            });
            RegisterCSR((ulong)CSRs.DCacheInfo, () => (ulong)dCacheInfo, value => dCacheInfo = (uint)value);

            InstallCustomInstruction(pattern: "00000000000000000101000000001111", handler: HandleFlushDataCacheInstruction);
        }
        public VexRiscv(Core.Machine machine, uint hartId = 0, IRiscVTimeProvider timeProvider = null, PrivilegeArchitecture privilegeArchitecture = PrivilegeArchitecture.Priv1_09, string cpuType = "rv32im") : base(timeProvider, cpuType, machine, hartId, privilegeArchitecture, Endianess.LittleEndian)
        {
            TlibSetCsrValidation(0);

            RegisterCSR((ulong)CSRs.MachineIrqMask, () => (ulong)machineInterrupts.Mask, value =>
            {
                lock (locker)
                {
                    machineInterrupts.Mask = (uint)value;
                    this.Log(LogLevel.Noisy, "Machine IRQ mask set to 0x{0:X}", machineInterrupts.Mask);
                    Update();
                }
            });
            RegisterCSR((ulong)CSRs.MachineIrqPending, () => (ulong)machineInterrupts.Pending, value =>
            {
                lock (locker)
                {
                    machineInterrupts.Pending = (uint)value;
                    this.Log(LogLevel.Noisy, "Machine IRQ pending set to 0x{0:X}", machineInterrupts.Pending);
                    Update();
                }
            });
            RegisterCSR((ulong)CSRs.SupervisorIrqMask, () => (ulong)supervisorInterrupts.Mask, value =>
            {
                lock (locker)
                {
                    supervisorInterrupts.Mask = (uint)value;
                    this.Log(LogLevel.Noisy, "Supervisor IRQ mask set to 0x{0:X}", supervisorInterrupts.Mask);
                    Update();
                }
            });
            RegisterCSR((ulong)CSRs.SupervisorIrqPending, () => (ulong)supervisorInterrupts.Pending, value =>
            {
                lock (locker)
                {
                    supervisorInterrupts.Pending = (uint)value;
                    this.Log(LogLevel.Noisy, "Supervisor IRQ pending set to 0x{0:X}", supervisorInterrupts.Pending);
                    Update();
                }
            });
            RegisterCSR((ulong)CSRs.DCacheInfo, () => (ulong)dCacheInfo, value => dCacheInfo = (uint)value);
        }
        public Minerva(Core.Machine machine, uint hartId = 0, IRiscVTimeProvider timeProvider = null) : base(timeProvider, "rv32i", machine, hartId, PrivilegeArchitecture.Priv1_09, Endianess.LittleEndian)
        {
            TlibSetCsrValidation(0);

            RegisterCSR((ulong)CSRs.IrqMask, () => (ulong)irqMask, value =>
            {
                lock (locker)
                {
                    irqMask = (uint)value;
                    this.Log(LogLevel.Noisy, "IRQ mask set to 0x{0:X}", irqMask);
                    Update();
                }
            });
            RegisterCSR((ulong)CSRs.IrqPending, () => (ulong)irqPending, value =>
            {
                lock (locker)
                {
                    irqPending = (uint)value;
                    this.Log(LogLevel.Noisy, "IRQ pending set to 0x{0:X}", irqPending);
                    Update();
                }
            });
        }
Exemple #9
0
 public IODevice(Core.Machine machine)
 {
     _ready = false;
     DataRegister = new Register(8);
     _machine = machine;
 }