public static void RunTest()
{
DesignContext.Reset();
TestHLS_ALU_Testbench tb = new TestHLS_ALU_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(10.0, ETimeUnit.us));
DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_TestHLS_ALU", "TestHLS_ALU");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);;
var eng = SynthesisEngine.Create(
DesignContext.Instance, new DocumentationProject(@".\hdl_out_TestHLS_ALU\doc"));
eng.Synthesize(new DocumentationGenerator());
project.Save();
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_ALU_Testbench tb = new TestHLS_ALU_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(10.0, ETimeUnit.us));
DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_TestHLS_ALU", "TestHLS_ALU");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen); ;
var eng = SynthesisEngine.Create(
DesignContext.Instance, new DocumentationProject(@".\hdl_out_TestHLS_ALU\doc"));
eng.Synthesize(new DocumentationGenerator());
project.Save();
}
static void Main(string[] args)
{
Console.WriteLine("SystemSharp test cases");
Console.WriteLine();
try
{
Console.WriteLine("Part 1: Basic data structures");
Console.WriteLine(" testing SystemSharp.Collections.EmilStefanov.DisjointSets");
SystemSharp.Collections.EmilStefanov.Test.DisjointSetsTester.RunTests();
Console.WriteLine(" testing fixed point math");
TestFixPoint.RunTest();
Console.WriteLine("Part 2: Design analysis and synthesis");
TestDesign1.RunTest();
TestRegPipe.RunTest();
TestAddMul0.RunTest();
TestAddMul1.RunTest();
TestAddMul2.RunTest();
Mod2TestDesign.Run();
TestConcatTestbench.Run();
Console.WriteLine("Part 3: Compiler");
CompilerTest.Testbench.RunTest();
Console.WriteLine("Part 4: Component tests");
ALUTestDesign.Run();
Mod2TestDesign.Run();
Test_SinCosLUT_Testbench.RunTest();
Console.WriteLine("Part 5: HLS");
TestHLS_PortAccess_Testbench.RunTest();
TestHLS_ALU_Testbench.RunTest();
TestHLS_FPU_Testbench.RunTest();
TestHLS_Cordic_Testbench.RunTest();
TestHLS_CordicSqrt_Testbench.RunTest();
TestHLS_CFlow_Testbench.RunTest();
TestHLS_CFlow2_Testbench.RunTest();
TestHLS_VanDerPol_Testbench.RunTest();
TestHLSTestbench1.RunTest();
TestHLS_SFixDiv.RunTest();
TestHLS_SinCosLUT_Testbench.RunTest();
Console.WriteLine("Part 6: File writing");
FileWriterTestbench.RunTest();
Console.WriteLine();
Console.WriteLine("Test passed");
}
catch (Exception e)
{
Console.WriteLine("Test failed: " + e.Message);
}
}