static void Main(string[] args)
{
///default values
int cycles = 100;
///elaborate
SimpleCounterTestbench tb = new SimpleCounterTestbench();
DesignContext.Instance.Elaborate();
///print out config
Console.WriteLine("#cycles: " + cycles);
///simulate
DesignContext.Instance.Simulate(cycles * SimpleCounterTestbench.ClockPeriod);
///notify completion
Console.WriteLine("Done. [ #cycles = " + cycles + " ]");
#if RUNANALYSIS
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_output", "SimpleCounter");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project_SC = new XilinxProject(@".\SystemC_output", "SimpleCounter");
project_SC.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project_SC.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project_SC.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project_SC.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project_SC.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
SystemCGenerator codeGen_SC = new SystemCGenerator();
SynthesisEngine.Create(DesignContext.Instance, project_SC).Synthesize(codeGen_SC);
project_SC.Save();
#endif
}
public SystemCStatementsGen(IndentedTextWriter tw, SystemCGenerator SysCg)
{
_tw = tw;
_SysCg = SysCg;
}
public static void Run()
{
Testbench tb = new Testbench();
DesignContext.Instance.Elaborate();
///remember start time
Start = System.DateTime.Now.Ticks;
DesignContext.Instance.Simulate(Cycles * Testbench.ClockCycle);
#if RUNANALYSIS
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_output", "Arbiter");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project_SC = new XilinxProject(@".\SystemC_output", "SimpleCounter");
project_SC.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project_SC.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project_SC.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project_SC.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project_SC.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
SystemCGenerator codeGen_SC = new SystemCGenerator();
SynthesisEngine.Create(DesignContext.Instance, project_SC).Synthesize(codeGen_SC);
project_SC.Save();
#endif
}
public LiteralStringifier(SystemCGenerator SysCg, LiteralReference.EMode mode)
{
_SysCg = SysCg;
Mode = mode;
}
