/// <summary>
/// Creates the default include region for a component
/// </summary>
/// <returns>The component include region.</returns>
/// <param name="config">The render configuration.</param>
/// <param name="indentation">The template indentation level.</param>
public static string CreateComponentInclude(RenderConfig config, int indentation)
{
string template;
if (config.DEVICE_VENDOR == FPGAVendor.Xilinx)
{
template = $@"
library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
";
}
else
{
template = string.Empty;
}
return(ReIndentTemplate(template, indentation));
}
/// <summary>
/// Performs the VHDL rendering.
/// </summary>
/// <param name="simulation">The simulation instance to parse.</param>
/// <param name="targetfolder">The folder where the output is stored.</param>
/// <param name="backupfolder">The folder where backups are stored.</param>
/// <param name="csvtracename">The name of the CSV trace file.</param>
/// <param name="customfiles">A list of VHDL files to include in the Makefile, without the VHDL extension</param>
/// <param name="config">The device and render configuration</param>
public static void Render(Simulation simulation, string targetfolder, string backupfolder = null, string csvtracename = null, IEnumerable <string> customfiles = null, RenderConfig config = null)
{
new RenderState(simulation, targetfolder, backupfolder, csvtracename, customfiles, config).Render();
}
