public PCIDevice(uint bus, uint slot, uint function)
{
this.bus = bus;
this.slot = slot;
this.function = function;
VendorID = ReadRegister16((byte)Config.VendorID);
DeviceID = ReadRegister16((byte)Config.DeviceID);
Command = ReadRegister16((byte)Config.Command);
Status = ReadRegister16((byte)Config.Status);
RevisionID = ReadRegister8((byte)Config.RevisionID);
ProgIF = ReadRegister8((byte)Config.ProgIF);
Subclass = ReadRegister8((byte)Config.SubClass);
ClassCode = ReadRegister8((byte)Config.Class);
SecondaryBusNumber = ReadRegister8((byte)Config.SecondaryBusNo);
HeaderType = (PCIHeaderType)ReadRegister8((byte)Config.HeaderType);
BIST = (PCIBist)ReadRegister8((byte)Config.BIST);
InterruptPIN = (PCIInterruptPIN)ReadRegister8((byte)Config.InterruptPIN);
DeviceExists = (uint)VendorID != 0xFFFF && (uint)DeviceID != 0xFFFF;
if (HeaderType == PCIHeaderType.Normal)
{
BaseAddressBar = new PCIBaseAddressBar[6];
BaseAddressBar[0] = new PCIBaseAddressBar(ReadRegister32(0x10));
BaseAddressBar[1] = new PCIBaseAddressBar(ReadRegister32(0x14));
BaseAddressBar[2] = new PCIBaseAddressBar(ReadRegister32(0x18));
BaseAddressBar[3] = new PCIBaseAddressBar(ReadRegister32(0x1C));
BaseAddressBar[4] = new PCIBaseAddressBar(ReadRegister32(0x20));
BaseAddressBar[5] = new PCIBaseAddressBar(ReadRegister32(0x24));
}
}
public PCIDeviceBridge(uint bus, uint slot, uint function)
: base(bus, slot, function)
{
BaseAddresses = new PCIBaseAddressBar[2];
BaseAddresses[0] = new PCIBaseAddressBar(ReadRegister32(0x10));
BaseAddresses[1] = new PCIBaseAddressBar(ReadRegister32(0x14));
PrimaryBusNumber = ReadRegister8(0x18);
SecondaryBusNumber = ReadRegister8(0x19);
SubordinateBusNumber = ReadRegister8(0x1A);
SecondaryLatencyTimer = ReadRegister8(0x1B);
IOBase = ReadRegister8(0x1C);
IOLimit = ReadRegister8(0x1D);
SecondaryStatus = ReadRegister16(0x1E);
MemoryBase = ReadRegister16(0x20);
MemoryLimit = ReadRegister16(0x22);
PrefatchableMemoryBase = ReadRegister16(0x24);
PrefatchableMemoryLimit = ReadRegister16(0x26);
PrefatchableBaseUpper32 = ReadRegister32(0x28);
PrefatchableLimitUpper32 = ReadRegister32(0x2C);
IOBaseUpper16 = ReadRegister16(0x30);
IOLimitUpper16 = ReadRegister16(0x32);
CapabilityPointer = ReadRegister8(0x34);
ExpansionROMBaseAddress = ReadRegister32(0x38);
BridgeControl = ReadRegister16(0x3E);
}
public PCIDeviceBridge(uint bus, uint slot, uint function)
: base(bus, slot, function)
{
BaseAddresses = new PCIBaseAddressBar[2];
BaseAddresses[0] = new PCIBaseAddressBar(ReadRegister32(0x10));
BaseAddresses[1] = new PCIBaseAddressBar(ReadRegister32(0x14));
PrimaryBusNumber = ReadRegister8(0x18);
SecondaryBusNumber = ReadRegister8(0x19);
SubordinateBusNumber = ReadRegister8(0x1A);
SecondaryLatencyTimer = ReadRegister8(0x1B);
IOBase = ReadRegister8(0x1C);
IOLimit = ReadRegister8(0x1D);
SecondaryStatus = ReadRegister16(0x1E);
MemoryBase = ReadRegister16(0x20);
MemoryLimit = ReadRegister16(0x22);
PrefatchableMemoryBase = ReadRegister16(0x24);
PrefatchableMemoryLimit = ReadRegister16(0x26);
PrefatchableBaseUpper32 = ReadRegister32(0x28);
PrefatchableLimitUpper32 = ReadRegister32(0x2C);
IOBaseUpper16 = ReadRegister16(0x30);
IOLimitUpper16 = ReadRegister16(0x32);
CapabilityPointer = ReadRegister8(0x34);
ExpansionROMBaseAddress = ReadRegister32(0x38);
BridgeControl = ReadRegister16(0x3E);
}
public PCIDeviceNormal(uint bus, uint slot, uint function)
: base(bus, slot, function)
{
BaseAddresses = new PCIBaseAddressBar[6];
BaseAddresses[0] = new PCIBaseAddressBar(ReadRegister32(0x10));
BaseAddresses[1] = new PCIBaseAddressBar(ReadRegister32(0x14));
BaseAddresses[2] = new PCIBaseAddressBar(ReadRegister32(0x18));
BaseAddresses[3] = new PCIBaseAddressBar(ReadRegister32(0x1C));
BaseAddresses[4] = new PCIBaseAddressBar(ReadRegister32(0x20));
BaseAddresses[5] = new PCIBaseAddressBar(ReadRegister32(0x24));
CardbusCISPointer = ReadRegister32(0x28);
SubsystemVendorID = ReadRegister16(0x2C);
SubsystemID = ReadRegister16(0x2E);
ExpansionROMBaseAddress = ReadRegister32(0x30);
CapabilitiesPointer = ReadRegister8(0x34);
MinGrant = ReadRegister8(0x3E);
MaxLatency = ReadRegister8(0x3F);
}
public PCIDeviceNormal(uint bus, uint slot, uint function)
: base(bus, slot, function)
{
BaseAddresses = new PCIBaseAddressBar[6];
BaseAddresses[0] = new PCIBaseAddressBar(ReadRegister32(0x10));
BaseAddresses[1] = new PCIBaseAddressBar(ReadRegister32(0x14));
BaseAddresses[2] = new PCIBaseAddressBar(ReadRegister32(0x18));
BaseAddresses[3] = new PCIBaseAddressBar(ReadRegister32(0x1C));
BaseAddresses[4] = new PCIBaseAddressBar(ReadRegister32(0x20));
BaseAddresses[5] = new PCIBaseAddressBar(ReadRegister32(0x24));
CardbusCISPointer = ReadRegister32(0x28);
SubsystemVendorID = ReadRegister16(0x2C);
SubsystemID = ReadRegister16(0x2E);
ExpansionROMBaseAddress = ReadRegister32(0x30);
CapabilitiesPointer = ReadRegister8(0x34);
MinGrant = ReadRegister8(0x3E);
MaxLatency = ReadRegister8(0x3F);
}