void dma_write()
{
LOG("{0}\n", "dma_write");
offs_t offset = m_channel[m_current_channel].m_address;
switch (MODE_TRANSFER_MASK)
{
case MODE_TRANSFER_VERIFY:
{
LOGTFR(" - MODE TRANSFER VERIFY");
uint8_t v1 = m_in_memr_cb.op(offset);
if (false && m_temp != v1)
{
logerror("verify error {0} vs. {1}\n", m_temp, v1);
}
break;
}
case MODE_TRANSFER_WRITE:
LOGTFR(" - MODE TRANSFER WRITE");
m_out_memw_cb.op(offset, m_temp);
break;
case MODE_TRANSFER_READ:
LOGTFR(" - MODE TRANSFER READ");
m_out_iow_cb[m_current_channel].op(offset, m_temp);
break;
}
LOGTFR(" channel {0} Offset {1}: {2} {3}\n", m_current_channel, offset, m_temp, m_channel[m_current_channel].m_count);
}
//-------------------------------------------------
// write_mode0 -
//-------------------------------------------------
void write_mode0(int port, byte data)
{
if (port_mode(port) == MODE_OUTPUT)
{
// latch output data
m_output[port] = data;
// write data to port
if (port == PORT_A)
{
m_out_pa_cb.op((offs_t)0, m_output[port]);
}
else if (port == PORT_B)
{
m_out_pb_cb.op((offs_t)0, m_output[port]);
}
else
{
m_out_pc_cb.op((offs_t)0, m_output[port]);
}
}
}
// internal helpers
//-------------------------------------------------
// update_bit - update one of the eight output
// lines with a new data bit
//-------------------------------------------------
void update_bit()
{
// first verify that the selected bit is actually changing
if (BIT(m_q, m_address) == (m_data ? 1 : 0))
{
return;
}
if (!m_clear)
{
// update selected bit with new data
m_q = (byte)((m_q & ~(1 << m_address)) | ((m_data ? 1 : 0) << m_address));
}
else
{
// clear any other bit that was formerly set
clear_outputs(0);
m_q = (byte)((m_data ? 1 : 0) << m_address);
}
// update output line via callback
if (!m_q_out_cb[m_address].isnull())
{
m_q_out_cb[m_address].op(m_data ? 1 : 0);
}
// update parallel output
if (!m_parallel_out_cb.isnull())
{
m_parallel_out_cb.op(0, m_q, (byte)(1 << m_address));
}
// do some logging
if (LOG_ALL_WRITES || (LOG_UNDEFINED_WRITES && m_q_out_cb[m_address].isnull() && m_parallel_out_cb.isnull()))
{
logerror("Q{0} {1} at {2}\n", m_address, m_data ? "set" : "cleared", machine().describe_context()); // Q%d %s at %s\n
}
}
void ay8910_write_reg(int r, int v)
{
//if (r >= 11 && r <= 13 ) printf("%d %x %02x\n", PSG->index, r, v);
m_regs[r] = (byte)v;
switch (r)
{
case AY_AFINE:
case AY_ACOARSE:
case AY_BFINE:
case AY_BCOARSE:
case AY_CFINE:
case AY_CCOARSE:
case AY_NOISEPER:
case AY_AVOL:
case AY_BVOL:
case AY_CVOL:
case AY_EFINE:
/* No action required */
break;
case AY_ECOARSE:
if ((v & 0x0f) > 0)
{
osd_printf_verbose("ECoarse\n");
}
/* No action required */
break;
case AY_ENABLE:
if ((m_last_enable == -1) ||
((m_last_enable & 0x40) != (m_regs[AY_ENABLE] & 0x40)))
{
/* write out 0xff if port set to input */
if (!m_port_a_write_cb.isnull())
{
m_port_a_write_cb.op((offs_t)0, (m_regs[AY_ENABLE] & 0x40) != 0 ? m_regs[AY_PORTA] : (byte)0xff);
}
}
if ((m_last_enable == -1) ||
((m_last_enable & 0x80) != (m_regs[AY_ENABLE] & 0x80)))
{
/* write out 0xff if port set to input */
if (!m_port_b_write_cb.isnull())
{
m_port_b_write_cb.op((offs_t)0, (m_regs[AY_ENABLE] & 0x80) != 0 ? m_regs[AY_PORTB] : (byte)0xff);
}
}
m_last_enable = m_regs[AY_ENABLE];
break;
case AY_ESHAPE:
if ((v & 0x0f) > 0)
{
osd_printf_verbose("EShape\n");
}
m_attack = (m_regs[AY_ESHAPE] & 0x04) != 0 ? m_env_step_mask : (byte)0x00;
if ((m_regs[AY_ESHAPE] & 0x08) == 0)
{
/* if Continue = 0, map the shape to the equivalent one which has Continue = 1 */
m_hold = 1;
m_alternate = m_attack;
}
else
{
m_hold = (byte)(m_regs[AY_ESHAPE] & 0x01);
m_alternate = (byte)(m_regs[AY_ESHAPE] & 0x02);
}
m_env_step = (sbyte)m_env_step_mask;
m_holding = 0;
m_env_volume = (UInt32)(m_env_step ^ m_attack);
break;
case AY_PORTA:
if ((m_regs[AY_ENABLE] & 0x40) != 0)
{
if (!m_port_a_write_cb.isnull())
{
m_port_a_write_cb.op((offs_t)0, m_regs[AY_PORTA]);
}
else
{
logerror("warning: unmapped write {0} to {1} Port A\n", v, name()); // %02x
}
}
else
{
#if LOG_IGNORED_WRITES
logerror("warning: write %02x to %s Port A set as input - ignored\n", v, name());
#endif
}
break;
case AY_PORTB:
if ((m_regs[AY_ENABLE] & 0x80) != 0)
{
if (!m_port_b_write_cb.isnull())
{
m_port_b_write_cb.op((offs_t)0, m_regs[AY_PORTB]);
}
else
{
logerror("warning: unmapped write {0} to {1} Port B\n", v, name()); // %02x
}
}
else
{
#if LOG_IGNORED_WRITES
logerror("warning: write %02x to %s Port B set as input - ignored\n", v, name());
#endif
}
break;
}
}
//WRITE8_MEMBER( namco_53xx_device::P_w )
public void P_w(address_space space, offs_t offset, u8 data, u8 mem_mask = 0xff)
{
m_p.op(space, 0, data);
}
// device_execute_interface overrides
//virtual UINT32 execute_min_cycles() const { return 1; }
//virtual UINT32 execute_max_cycles() const { return 3; }
//virtual UINT32 execute_input_lines() const { return 1; }
public void device_execute_interface_execute_run()
{
while (m_icountRef.i > 0)
{
byte opcode;
byte arg;
byte oc;
/* fetch the opcode */
debugger_instruction_hook(GETPC());
opcode = READOP(GETPC());
/* increment the PC */
INCPC();
/* start with instruction doing 1 cycle */
oc = 1;
switch (opcode)
{
case 0x00: /* nop ZCS:...*/
m_st = 1;
break;
case 0x01: /* outO ZCS:...*/
m_write_o.op((byte)pla(m_A, TEST_CF()));
m_st = 1;
break;
case 0x02: /* outP ZCS:... */
m_write_p.op(m_A);
m_st = 1;
break;
case 0x03: /* outR ZCS:... */
arg = m_Y;
m_write_r[arg & 3].op(m_A);
m_st = 1;
break;
case 0x04: /* tay ZCS:... */
m_Y = m_A;
m_st = 1;
break;
case 0x05: /* tath ZCS:... */
m_TH = m_A;
m_st = 1;
break;
case 0x06: /* tatl ZCS:... */
m_TL = m_A;
m_st = 1;
break;
case 0x07: /* tas ZCS:... */
m_SB = m_A;
m_st = 1;
break;
case 0x08: /* icy ZCS:x.x */
m_Y++;
UPDATE_ST_C(m_Y);
m_Y &= 0x0f;
UPDATE_ZF(m_Y);
break;
case 0x09: /* icm ZCS:x.x */
arg = RDMEM(GETEA());
arg++;
UPDATE_ST_C(arg);
arg &= 0x0f;
UPDATE_ZF(arg);
WRMEM(GETEA(), arg);
break;
case 0x0a: /* stic ZCS:x.x */
WRMEM(GETEA(), m_A);
m_Y++;
UPDATE_ST_C(m_Y);
m_Y &= 0x0f;
UPDATE_ZF(m_Y);
break;
case 0x0b: /* x ZCS:x.. */
arg = RDMEM(GETEA());
WRMEM(GETEA(), m_A);
m_A = arg;
UPDATE_ZF(m_A);
m_st = 1;
break;
case 0x0c: /* rol ZCS:xxx */
m_A <<= 1;
m_A |= (byte)TEST_CF();
UPDATE_ST_C(m_A);
m_cf = (byte)(m_st ^ 1);
m_A &= 0x0f;
UPDATE_ZF(m_A);
break;
case 0x0d: /* l ZCS:x.. */
m_A = RDMEM(GETEA());
UPDATE_ZF(m_A);
m_st = 1;
break;
case 0x0e: /* adc ZCS:xxx */
arg = RDMEM(GETEA());
arg += m_A;
arg += (byte)TEST_CF();
UPDATE_ST_C(arg);
m_cf = (byte)(m_st ^ 1);
m_A = (byte)(arg & 0x0f);
UPDATE_ZF(m_A);
break;
case 0x0f: /* and ZCS:x.x */
m_A &= RDMEM(GETEA());
UPDATE_ZF(m_A);
m_st = (byte)(m_zf ^ 1);
break;
case 0x10: /* daa ZCS:.xx */
if (TEST_CF() != 0 || m_A > 9)
{
m_A += 6;
}
UPDATE_ST_C(m_A);
m_cf = (byte)(m_st ^ 1);
m_A &= 0x0f;
break;
case 0x11: /* das ZCS:.xx */
if (TEST_CF() != 0 || m_A > 9)
{
m_A += 10;
}
UPDATE_ST_C(m_A);
m_cf = (byte)(m_st ^ 1);
m_A &= 0x0f;
break;
case 0x12: /* inK ZCS:x.. */
m_A = (byte)(m_read_k.op() & 0x0f);
UPDATE_ZF(m_A);
m_st = 1;
break;
case 0x13: /* inR ZCS:x.. */
arg = m_Y;
m_A = (byte)(m_read_r[arg & 3].op() & 0x0f);
UPDATE_ZF(m_A);
m_st = 1;
break;
case 0x14: /* tya ZCS:x.. */
m_A = m_Y;
UPDATE_ZF(m_A);
m_st = 1;
break;
case 0x15: /* ttha ZCS:x.. */
m_A = m_TH;
UPDATE_ZF(m_A);
m_st = 1;
break;
case 0x16: /* ttla ZCS:x.. */
m_A = m_TL;
UPDATE_ZF(m_A);
m_st = 1;
break;
case 0x17: /* tsa ZCS:x.. */
m_A = m_SB;
UPDATE_ZF(m_A);
m_st = 1;
break;
case 0x18: /* dcy ZCS:..x */
m_Y--;
UPDATE_ST_C(m_Y);
m_Y &= 0x0f;
break;
case 0x19: /* dcm ZCS:x.x */
arg = RDMEM(GETEA());
arg--;
UPDATE_ST_C(arg);
arg &= 0x0f;
UPDATE_ZF(arg);
WRMEM(GETEA(), arg);
break;
case 0x1a: /* stdc ZCS:x.x */
WRMEM(GETEA(), m_A);
m_Y--;
UPDATE_ST_C(m_Y);
m_Y &= 0x0f;
UPDATE_ZF(m_Y);
break;
case 0x1b: /* xx ZCS:x.. */
arg = m_X;
m_X = m_A;
m_A = arg;
UPDATE_ZF(m_A);
m_st = 1;
break;
case 0x1c: /* ror ZCS:xxx */
m_A |= (byte)(TEST_CF() << 4);
UPDATE_ST_C((byte)(m_A << 4));
m_cf = (byte)(m_st ^ 1);
m_A >>= 1;
m_A &= 0x0f;
UPDATE_ZF(m_A);
break;
case 0x1d: /* st ZCS:x.. */
WRMEM(GETEA(), m_A);
m_st = 1;
break;
case 0x1e: /* sbc ZCS:xxx */
arg = RDMEM(GETEA());
arg -= m_A;
arg -= (byte)TEST_CF();
UPDATE_ST_C(arg);
m_cf = (byte)(m_st ^ 1);
m_A = (byte)(arg & 0x0f);
UPDATE_ZF(m_A);
break;
case 0x1f: /* or ZCS:x.x */
m_A |= RDMEM(GETEA());
UPDATE_ZF(m_A);
m_st = (byte)(m_zf ^ 1);
break;
case 0x20: /* setR ZCS:... */
arg = m_read_r[m_Y / 4].op();
m_write_r[m_Y / 4].op((byte)(arg | (1 << (m_Y % 4))));
m_st = 1;
break;
case 0x21: /* setc ZCS:.xx */
m_cf = 1;
m_st = 1;
break;
case 0x22: /* rstR ZCS:... */
arg = m_read_r[m_Y / 4].op();
m_write_r[m_Y / 4].op((byte)(arg & ~(1 << (m_Y % 4))));
m_st = 1;
break;
case 0x23: /* rstc ZCS:.xx */
m_cf = 0;
m_st = 1;
break;
case 0x24: /* tstr ZCS:..x */
arg = m_read_r[m_Y / 4].op();
m_st = (arg & (1 << (m_Y % 4))) != 0 ? (byte)0 : (byte)1;
break;
case 0x25: /* tsti ZCS:..x */
m_st = (byte)(m_nf ^ 1);
break;
case 0x26: /* tstv ZCS:..x */
m_st = (byte)(m_vf ^ 1);
m_vf = 0;
break;
case 0x27: /* tsts ZCS:..x */
m_st = (byte)(m_sf ^ 1);
if (m_sf != 0)
{
/* re-enable the timer if we disabled it previously */
if (m_SBcount >= mb88_cpu_device.SERIAL_DISABLE_THRESH)
{
m_serial.adjust(attotime.from_hz(clock() / mb88_cpu_device.SERIAL_PRESCALE), 0, attotime.from_hz(clock() / mb88_cpu_device.SERIAL_PRESCALE));
}
m_SBcount = 0;
}
m_sf = 0;
break;
case 0x28: /* tstc ZCS:..x */
m_st = (byte)(m_cf ^ 1);
break;
case 0x29: /* tstz ZCS:..x */
m_st = (byte)(m_zf ^ 1);
break;
case 0x2a: /* sts ZCS:x.. */
WRMEM(GETEA(), m_SB);
UPDATE_ZF(m_SB);
m_st = 1;
break;
case 0x2b: /* ls ZCS:x.. */
m_SB = RDMEM(GETEA());
UPDATE_ZF(m_SB);
m_st = 1;
break;
case 0x2c: /* rts ZCS:... */
m_SI = (byte)((m_SI - 1) & 3);
m_PC = (byte)(m_SP[m_SI] & 0x3f);
m_PA = (byte)((m_SP[m_SI] >> 6) & 0x1f);
m_st = 1;
break;
case 0x2d: /* neg ZCS: ..x */
m_A = (byte)((~m_A) + 1);
m_A &= 0x0f;
UPDATE_ST_Z(m_A);
break;
case 0x2e: /* c ZCS:xxx */
arg = RDMEM(GETEA());
arg -= m_A;
UPDATE_CF(arg);
arg &= 0x0f;
UPDATE_ST_Z(arg);
m_zf = (byte)(m_st ^ 1);
break;
case 0x2f: /* eor ZCS:x.x */
m_A ^= RDMEM(GETEA());
UPDATE_ST_Z(m_A);
m_zf = (byte)(m_st ^ 1);
break;
case 0x30:
case 0x31:
case 0x32:
case 0x33: /* sbit ZCS:... */
arg = RDMEM(GETEA());
WRMEM(GETEA(), (byte)(arg | (1 << (opcode & 3))));
m_st = 1;
break;
case 0x34:
case 0x35:
case 0x36:
case 0x37: /* rbit ZCS:... */
arg = RDMEM(GETEA());
WRMEM(GETEA(), (byte)(arg & ~(1 << (opcode & 3))));
m_st = 1;
break;
case 0x38:
case 0x39:
case 0x3a:
case 0x3b: /* tbit ZCS:... */
arg = RDMEM(GETEA());
m_st = (arg & (1 << (opcode & 3))) != 0 ? (byte)0 : (byte)1;
break;
case 0x3c: /* rti ZCS:... */
/* restore address and saved state flags on the top bits of the stack */
m_SI = (byte)((m_SI - 1) & 3);
m_PC = (byte)(m_SP[m_SI] & 0x3f);
m_PA = (byte)((m_SP[m_SI] >> 6) & 0x1f);
m_st = (byte)((m_SP[m_SI] >> 13) & 1);
m_zf = (byte)((m_SP[m_SI] >> 14) & 1);
m_cf = (byte)((m_SP[m_SI] >> 15) & 1);
break;
case 0x3d: /* jpa imm ZCS:..x */
m_PA = (byte)(READOP(GETPC()) & 0x1f);
m_PC = (byte)(m_A * 4);
oc = 2;
m_st = 1;
break;
case 0x3e: /* en imm ZCS:... */
update_pio_enable((byte)(m_pio | READOP(GETPC())));
INCPC();
oc = 2;
m_st = 1;
break;
case 0x3f: /* dis imm ZCS:... */
update_pio_enable((byte)(m_pio & ~(READOP(GETPC()))));
INCPC();
oc = 2;
m_st = 1;
break;
case 0x40:
case 0x41:
case 0x42:
case 0x43: /* setD ZCS:... */
arg = m_read_r[0].op();
arg |= (byte)(1 << (opcode & 3));
m_write_r[0].op(arg);
m_st = 1;
break;
case 0x44:
case 0x45:
case 0x46:
case 0x47: /* rstD ZCS:... */
arg = m_read_r[0].op();
arg &= (byte)(~(1 << (opcode & 3)));
m_write_r[0].op(arg);
m_st = 1;
break;
case 0x48:
case 0x49:
case 0x4a:
case 0x4b: /* tstD ZCS:..x */
arg = m_read_r[2].op();
m_st = (arg & (1 << (opcode & 3))) != 0 ? (byte)0 : (byte)1;
break;
case 0x4c:
case 0x4d:
case 0x4e:
case 0x4f: /* tba ZCS:..x */
m_st = (m_A & (1 << (opcode & 3))) != 0 ? (byte)0 : (byte)1;
break;
case 0x50:
case 0x51:
case 0x52:
case 0x53: /* xd ZCS:x.. */
arg = RDMEM((UInt32)(opcode & 3));
WRMEM((UInt32)(opcode & 3), m_A);
m_A = arg;
UPDATE_ZF(m_A);
m_st = 1;
break;
case 0x54:
case 0x55:
case 0x56:
case 0x57: /* xyd ZCS:x.. */
arg = RDMEM((UInt32)((opcode & 3) + 4));
WRMEM((UInt32)((opcode & 3) + 4), m_Y);
m_Y = arg;
UPDATE_ZF(m_Y);
m_st = 1;
break;
case 0x58:
case 0x59:
case 0x5a:
case 0x5b:
case 0x5c:
case 0x5d:
case 0x5e:
case 0x5f: /* lxi ZCS:x.. */
m_X = (byte)(opcode & 7);
UPDATE_ZF(m_X);
m_st = 1;
break;
case 0x60:
case 0x61:
case 0x62:
case 0x63:
case 0x64:
case 0x65:
case 0x66:
case 0x67: /* call imm ZCS:..x */
arg = READOP(GETPC());
INCPC();
oc = 2;
if (TEST_ST() != 0)
{
m_SP[m_SI] = GETPC();
m_SI = (byte)((m_SI + 1) & 3);
m_PC = (byte)(arg & 0x3f);
m_PA = (byte)(((opcode & 7) << 2) | (arg >> 6));
}
m_st = 1;
break;
case 0x68:
case 0x69:
case 0x6a:
case 0x6b:
case 0x6c:
case 0x6d:
case 0x6e:
case 0x6f: /* jpl imm ZCS:..x */
arg = READOP(GETPC());
INCPC();
oc = 2;
if (TEST_ST() != 0)
{
m_PC = (byte)(arg & 0x3f);
m_PA = (byte)(((opcode & 7) << 2) | (arg >> 6));
}
m_st = 1;
break;
case 0x70:
case 0x71:
case 0x72:
case 0x73:
case 0x74:
case 0x75:
case 0x76:
case 0x77:
case 0x78:
case 0x79:
case 0x7a:
case 0x7b:
case 0x7c:
case 0x7d:
case 0x7e:
case 0x7f: /* ai ZCS:xxx */
arg = (byte)(opcode & 0x0f);
arg += m_A;
UPDATE_ST_C(arg);
m_cf = (byte)(m_st ^ 1);
m_A = (byte)(arg & 0x0f);
UPDATE_ZF(m_A);
break;
case 0x80:
case 0x81:
case 0x82:
case 0x83:
case 0x84:
case 0x85:
case 0x86:
case 0x87:
case 0x88:
case 0x89:
case 0x8a:
case 0x8b:
case 0x8c:
case 0x8d:
case 0x8e:
case 0x8f: /* lxi ZCS:x.. */
m_Y = (byte)(opcode & 0x0f);
UPDATE_ZF(m_Y);
m_st = 1;
break;
case 0x90:
case 0x91:
case 0x92:
case 0x93:
case 0x94:
case 0x95:
case 0x96:
case 0x97:
case 0x98:
case 0x99:
case 0x9a:
case 0x9b:
case 0x9c:
case 0x9d:
case 0x9e:
case 0x9f: /* li ZCS:x.. */
m_A = (byte)(opcode & 0x0f);
UPDATE_ZF(m_A);
m_st = 1;
break;
case 0xa0:
case 0xa1:
case 0xa2:
case 0xa3:
case 0xa4:
case 0xa5:
case 0xa6:
case 0xa7:
case 0xa8:
case 0xa9:
case 0xaa:
case 0xab:
case 0xac:
case 0xad:
case 0xae:
case 0xaf: /* cyi ZCS:xxx */
arg = (byte)((opcode & 0x0f) - m_Y);
UPDATE_CF(arg);
arg &= 0x0f;
UPDATE_ST_Z(arg);
m_zf = (byte)(m_st ^ 1);
break;
case 0xb0:
case 0xb1:
case 0xb2:
case 0xb3:
case 0xb4:
case 0xb5:
case 0xb6:
case 0xb7:
case 0xb8:
case 0xb9:
case 0xba:
case 0xbb:
case 0xbc:
case 0xbd:
case 0xbe:
case 0xbf: /* ci ZCS:xxx */
arg = (byte)((opcode & 0x0f) - m_A);
UPDATE_CF(arg);
arg &= 0x0f;
UPDATE_ST_Z(arg);
m_zf = (byte)(m_st ^ 1);
break;
default: /* jmp ZCS:..x */
if (TEST_ST() != 0)
{
m_PC = (byte)(opcode & 0x3f);
}
m_st = 1;
break;
}
/* update cycle counts */
CYCLES(oc);
/* update interrupts, serial and timer flags */
update_pio(oc);
}
}