public static void RunTest()
{
DesignContext.Reset();
TestHLS_CordicSqrt_Testbench tb = new TestHLS_CordicSqrt_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(100.0, ETimeUnit.us));
DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
var docproj = new DocumentationProject(@".\hdl_out_TestHLSSqrt_Cordic\doc");
var project = new XilinxProject(@".\hdl_out_TestHLSSqrt_Cordic", "TestHLSSqrt_Cordic");
project.ISEVersion = EISEVersion._13_2;
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
//project.SkipIPCoreSynthesis = true;
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);
SynthesisEngine.Create(DesignContext.Instance, docproj).Synthesize(new DocumentationGenerator());
project.Save();
docproj.Save();
}
public static void RunTest()
{
DesignContext.Reset();
FixedPointSettings.GlobalDefaultRadix = 10;
var tb = new Test_SinCosLUT_Testbench(7, 8, 9, 0);
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(1.0, ETimeUnit.us));
DesignContext.Stop();
//XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_Test_SinCosLUT_Testbench", "Test_SinCosLUT_Testbench");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
project.TwinProject = new ModelsimProject(@".\hdl_out_Test_SinCosLUT_Testbench", "Test_SinCosLUT_Testbench");
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);
project.Save();
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_PortAccess_Testbench tb = new TestHLS_PortAccess_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(1.0, ETimeUnit.us));
DesignContext.Stop();
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_TestHLS_PortAccess", "TestHLS_PortAccess");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
project.SkipIPCoreSynthesis = true;
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);
project.Save();
}
public static void Run()
{
DesignContext.Reset();
Mod2TestDesign td = new Mod2TestDesign(3, 10, 2);
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(1.0, ETimeUnit.us));
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_ALUTestDesign", "ALUTestDesign");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.SetVHDLProfile();
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
}
public static void RunTest()
{
DesignContext.Reset();
var tb = new FileWriterTestbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(0.5, ETimeUnit.us));
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_WriteFile", "FileWriterDesign");
project.ISEVersion = EISEVersion._13_2;
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.SetVHDLProfile();
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
}
public static void Run()
{
DesignContext.Reset();
ALUTestDesign td = new ALUTestDesign(8, 8, 2);
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(0.5, ETimeUnit.us));
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_ALUTestDesign", "ALUTestDesign");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.SetVHDLProfile();
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_FPU_Testbench tb = new TestHLS_FPU_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(3.0, ETimeUnit.us));
DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_TestHLS_FPU", "TestHLS_FPU");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);
project.Save();
var eng = SynthesisEngine.Create(
DesignContext.Instance, new DocumentationProject(@".\hdl_out_TestHLS_FPU\doc"));
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_PortAccess_Testbench tb = new TestHLS_PortAccess_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(1.0, ETimeUnit.us));
DesignContext.Stop();
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_TestHLS_PortAccess", "TestHLS_PortAccess");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
project.SkipIPCoreSynthesis = true;
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);
project.Save();
}
/// <summary>
/// Synthesizes the design.
/// </summary>
/// <param name="destPath">target path which will contain the generated files</param>
/// <param name="designName">name of the design</param>
/// <param name="info">ISE information</param>
/// <param name="twinProject">optional twin project</param>
/// <param name="step">what stages of the overall flow to execute</param>
/// <returns>the generated ISE project</returns>
public XilinxProject Synthesize(string destPath, string designName, ISEInfo info,
IProject twinProject = null, EFlowStep step = EFlowStep.HDLGenAndIPCores)
{
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(destPath, designName)
{
TwinProject = twinProject
};
project.ISEVersion = info.VersionTag;
if (info.Path == null)
project.SkipIPCoreSynthesis = true;
else
project.ISEBinPath = info.Path;
project.PutProperty(EXilinxProjectProperties.DeviceFamily, Device.GetFamily());
project.PutProperty(EXilinxProjectProperties.Device, Device);
project.PutProperty(EXilinxProjectProperties.Package, Package);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, SpeedGrade);
project.SetVHDLProfile();
if (!step.HasFlag(EFlowStep.IPCores))
project.SkipIPCoreSynthesis = true;
project.TopLevelComponent = TopLevelComponent.Descriptor;
CreateUCF(project);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(GetComponentSet(), codeGen);
project.Save();
if (step.HasFlag(EFlowStep.XST) ||
step.HasFlag(EFlowStep.NGDBuild) ||
step.HasFlag(EFlowStep.Map) ||
step.HasFlag(EFlowStep.PAR) ||
step.HasFlag(EFlowStep.TRCE))
{
var flow = project.ConfigureFlow(TopLevelComponent);
flow.Start(step);
}
return project;
}