static void Main(string[] args)
{
Testbench tb = new Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(101 * Testbench.ClockPeriod);
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project_SC = new XilinxProject(@".\SystemC_output", "SimpleCounter");
project_SC.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project_SC.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project_SC.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project_SC.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project_SC.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
SystemCGenerator codeGen_SC = new SystemCGenerator();
SynthesisEngine.Create(DesignContext.Instance, project_SC).Synthesize(codeGen_SC);
project_SC.Save();
DesignContext.Instance.CompleteAnalysis();
// The actual compilation steps start here.
ProcessDescriptor euclid = tb.Descriptor.FindComponent("_gcd").FindProcess("Euclid");
XIL3Function asm = euclid.Implementation.Compile(DefaultInstructionSet.Instance).ToXIL3();
Console.WriteLine(asm);
}
public virtual XIL3Function Rewrite(XIL3Function func)
{
InInstructions = func.Instructions;
_orgSlotTypes = func.SlotTypes;
Rewrite();
return(new XIL3Function(func.Name, func.Arguments, func.Locals,
OutInstructions.ToArray(),
OutSlotTypes.ToArray()));
}
// scheduled for removal.
public XIL3Function ExecuteXILTransformations(XILSFunction fnasm)
{
fnasm.SanityCheck();
IList <XILSInstr> instrs = fnasm.Instructions.ToList();
foreach (IXILSRewriter rw in XILSTransformations)
{
instrs = rw.Rewrite(instrs);
fnasm = new XILSFunction(fnasm.Name, fnasm.Arguments, fnasm.Locals, instrs.ToArray());
fnasm.SanityCheck();
}
XIL3Function fnasm3 = fnasm.ToXIL3();
foreach (IXIL3Rewriter rw in XIL3Transformations)
{
fnasm3 = rw.Rewrite(fnasm3);
fnasm3.SanityCheck();
}
return(fnasm3);
}
public virtual XIL3Function Rewrite(XIL3Function func)
{
InInstructions = func.Instructions;
_orgSlotTypes = func.SlotTypes;
Rewrite();
return new XIL3Function(func.Name, func.Arguments, func.Locals,
OutInstructions.ToArray(),
OutSlotTypes.ToArray());
}
public override XIL3Function Rewrite(XIL3Function func)
{
_map = new Dictionary <XIL3Instr, XIL3Instr>(new XIL3Comparer(func));
_bbBoundaries = new HashSet <int>(func.GetBasicBlockBoundaries());
return(base.Rewrite(func));
}
public XIL3Comparer(XIL3Function func)
{
_func = func;
}
public XIL3Function Rewrite(XIL3Function func)
{
return(new CommonSubExpressionEliminator().Rewrite(func));
}
internal void ExtractFrom(XIL3Function func, XILSchedulingAdapter xsa)
{
if (FirstILIndex == null || LastILIndex == null)
{
IsValid = false;
return;
}
var firstInstr = func.Instructions.Where(i => i.CILRef >= FirstILIndex).FirstOrDefault();
var lastInstr = func.Instructions.Where(i => i.CILRef <= LastILIndex).LastOrDefault();
if (firstInstr == null || lastInstr == null)
{
FirstCStep = 1;
LastCStep = 0;
IsValid = false;
return;
}
FirstCStep = xsa.CStep[firstInstr];
LastCStep = xsa.CStep[lastInstr];
IsValid = true;
}
public _3ACtoStkImpl(XIL3Function func)
{
_inFunc = func;
}
/// <summary>
/// Executes the HLS design flow.
/// </summary>
/// <param name="design">the design</param>
/// <param name="host">the hosting component</param>
/// <param name="proc">the process being subject to HLS</param>
/// <param name="targetProject">the target project</param>
/// <remarks>Inside the hosting component, the process will be replaced by the synthesized hardware.</remarks>
public void Execute(DesignContext design, Component host, ProcessDescriptor proc, IProject targetProject)
{
Contract.Requires <ArgumentNullException>(design != null);
Contract.Requires <ArgumentNullException>(host != null);
Contract.Requires <ArgumentNullException>(proc != null);
Contract.Requires <ArgumentNullException>(targetProject != null);
design.CurrentProcess = proc.Instance;
var clk = proc.Sensitivity[0];
SignalBase clkI;
var sdClk = clk as SignalDescriptor;
if (sdClk == null)
{
clkI = ((SignalDescriptor)((PortDescriptor)clk).BoundSignal).Instance;
}
else
{
clkI = sdClk.Instance;
}
var state = new HLSState(this, design, host, proc, targetProject);
proc.AddAttribute(state);
if (_beginHLS != null)
{
_beginHLS(state);
}
var dpb = new DefaultDatapathBuilder(host, clkI, proc.Name);
state.InterconnectBuilder = InterconnectBuilder.Create(host, dpb.ICBinder);
state.ControlpathBuilder = ControlPathBuilder.Create(host, dpb.FUBinder);
state.ControlpathBuilder.PersonalizePlan(this);
do
{
XILSFunction fnasm;
if (!proc.HasAttribute <XILSFunction>())
{
var func = proc.Implementation;
IEnumerable <Function> inlinedFunctions;
func = func.InlineCalls(out inlinedFunctions);
if (ConvertFieldsToLocals)
{
Variable[] newLocals;
func = func.ConvertFieldsToLocals(out newLocals);
}
state.PreprocessedFunction = func;
fnasm = state.PreprocessedFunction.Compile(DefaultInstructionSet.Instance);
}
else
{
fnasm = proc.QueryAttribute <XILSFunction>();
}
fnasm.SanityCheck();
state.XILSInput = fnasm;
IList <XILSInstr> instrs = state.XILSInput.Instructions.ToList();
foreach (var rw in XILSTransformations)
{
instrs = rw.Rewrite(instrs);
fnasm = new XILSFunction(fnasm.Name, fnasm.Arguments, fnasm.Locals, instrs.ToArray());
fnasm.SanityCheck();
}
state.XILSTransformed = fnasm;
XIL3Function fnasm3 = fnasm.ToXIL3();
state.XIL3Input = fnasm3;
foreach (IXIL3Rewriter rw in XIL3Transformations)
{
fnasm3 = rw.Rewrite(fnasm3);
fnasm3.SanityCheck();
}
state.XIL3Transformed = fnasm3;
state.NotifyProgress(EHLSProgress.Compiled);
} while (state._repeat);
if (state._cancel)
{
return;
}
SchedulingConstraints constraints;
do
{
var xmm = new XILMapperManager();
foreach (var dpu in Enumerable.Reverse(XILMappers))
{
xmm.AddMapper(dpu);
}
DesignContext.Push();
var xilsa = new XILSchedulingAdapter(state.XIL3Transformed, xmm, host, targetProject);
if (AllocationPolicy != null)
{
xilsa.Allocator.Policy = AllocationPolicy.Create();
}
if (_onFUCreated != null)
{
xilsa.Allocator.OnFUAllocation += _onFUCreated;
}
state.SchedulingAdapter = xilsa;
state.NotifyProgress(EHLSProgress.AboutToSchedule);
constraints = SchedulingConstraints;
if (constraints == null)
{
if (proc.Implementation != null)
{
constraints = proc.Implementation.QueryAttribute <SchedulingConstraints>();
}
if (constraints == null)
{
constraints = new SchedulingConstraints();
}
}
state.Constraints = constraints;
if (constraints.MinimizeNumberOfFUs)
{
foreach (var instr in state.XIL3Transformed.Instructions)
{
xilsa.SetMaxFUAllocation(xilsa.IClass[instr], 1);
}
}
Scheduler.Schedule(xilsa.CFG, constraints, xilsa);
DesignContext.Pop();
state.NotifyProgress(EHLSProgress.Scheduled);
} while (state._repeat);
ComputeCStepsForBranchTargets(state.SchedulingAdapter);
do
{
state.ControlpathBuilder.PrepareAllocation(state.SchedulingAdapter.ComputeCStepCount());
var flowSpec = state.SchedulingAdapter.Allocate(dpb);
state.RawFlows = flowSpec;
var realFlow = new FlowMatrix();
state.InterconnectBuilder.CreateInterconnect(flowSpec, realFlow);
state.RealFlows = realFlow;
state.NotifyProgress(EHLSProgress.InterconnectCreated);
} while (state._repeat);
if (state._cancel)
{
return;
}
Debug.Assert(state.RealFlows.FlowSources.All(sr => sr.Desc.Owner != null));
Debug.Assert(state.RealFlows.FlowTargets.All(sr => sr.Desc.Owner != null));
do
{
state.ControlpathBuilder.CreateControlpath(state.RealFlows, proc.Name);
foreach (var prof in constraints.Profilers)
{
prof.ExtractFrom(state.XIL3Transformed, state.SchedulingAdapter);
}
state.NotifyProgress(EHLSProgress.ControlpathCreated);
} while (state._repeat);
if (state._cancel)
{
return;
}
}
