public VerilogTokenTag(VerilogTokenTypes type)
{
VerilogGlobals.PerfMon.VerilogTokenTag_Count++;
this.type = type;
}
/// <summary>
/// Process_UndefinedState_For
/// </summary>
/// <param name="ItemText"></param>
private static void Process_UndefinedState_For(string ItemText)
{
switch (ItemText)
{
case "":
// ignoring trimmed spaces / blanks
break;
case "module":
// we're naming a module
BuildHoverState = BuildHoverStates.ModuleStart;
thisModuleDeclarationText = ItemText;
break;
case "input":
case "output":
case "inout":
case "wire":
case "reg":
case "localparam":
case "parameter":
// the same keywords could be used for module parameters, or variables:
switch (BuildHoverState)
{
case BuildHoverStates.ModuleStart:
BuildHoverState = BuildHoverStates.ModuleParameterNaming;
break;
case BuildHoverStates.VariableMimicNaming: // comma-delimited types have the type copied (mimic) into hover text for each variable
BuildHoverState = BuildHoverStates.VariableNaming;
thisVariableDeclarationText = ItemText;
thisHoverName = ""; // we are no longer using the same type declaration, so reset to blank
break;
default:
BuildHoverState = BuildHoverStates.VariableNaming;
thisVariableDeclarationText = ItemText;
break;
}
thisVariableType = VerilogGlobals.VerilogTypes["variable_" + ItemText];
break;
case "endmodule":
// we're naming a module
BuildHoverState = BuildHoverStates.UndefinedState;
// this is likely a syntax error
break;
default:
if (VerilogVariables.ContainsKey(ItemText))
{
// a scope-level module name is defined, so treat it like a variable type
BuildHoverState = BuildHoverStates.VariableNaming; // actually, we are module naming. TODO different color for modules?
// a module instantiation will have the work "module" manually prepended
thisVariableDeclarationText = "module " + ItemText;
}
else
{
BuildHoverState = BuildHoverStates.UndefinedState;
}
break;
}
}
