protected override void DoCommandAction()
{
VHDLFile union = new VHDLFile("union_interface");
foreach (string vhdlFile in Modules)
{
VHDLParser p = new VHDLParser(vhdlFile);
foreach (VHDLParserEntity entity in p.GetEntities())
{
foreach (HDLEntitySignal signal in entity.InterfaceSignals)
{
int width = signal.MSB - signal.LSB + 1;
if (!union.Entity.HasSignal(signal.SignalName))
{
union.Entity.Add(signal.SignalName, width, Objects.PortMapper.MappingKind.External);
union.Entity.SetDirection(signal.SignalName, FPGA.FPGATypes.GetPortDirectionFromString(signal.SignalDirection));
}
else
{
union.Entity.SetSignalWidth(signal.SignalName, Math.Max(width, union.Entity.GetSignalWidth(signal.SignalName)));
}
}
}
}
OutputManager.WriteOutput("entity union_interface is port (");
OutputManager.WriteOutput(union.Entity.ToString());
OutputManager.WriteOutput("end union_interface;");
}
protected sealed override void DoCommandAction()
{
VHDLFile vhdlFile = new VHDLFile(EntityName);
InstantiationFilter = Regex.Replace(InstantiationFilter, "\\\"", "");
foreach (LibElemInst inst in LibraryElementInstanceManager.Instance.GetAllInstantiations().Where(i => Regex.IsMatch(i.InstanceName, InstantiationFilter)))
{
LibraryElement libElement = Objects.Library.Instance.GetElement(inst.LibraryElementName);
// add each component once
if (!vhdlFile.HasComponent(libElement.PrimitiveName))
{
vhdlFile.Add(new VHDLComponent(libElement));
}
vhdlFile.Add(new VHDLInstantiation(vhdlFile, inst, libElement, this));
}
// call base class implementation
PrintVHDLCode(vhdlFile);
}
protected override void PrintVHDLCode(VHDLFile vhdlFile)
{
// onle for ISE insert component declarations, in Vivado we use LUT6 primitves, and do not need component declartation
OutputManager.WriteVHDLOutput(vhdlFile.GetSubsystem(FPGA.FPGA.Instance.BackendType == FPGA.FPGATypes.BackendType.ISE));
}
protected override void PrintVHDLCode(VHDLFile vhdlFile)
{
OutputManager.WriteVHDLOutput(vhdlFile.GetSubsystemInstantiation());
}
protected abstract void PrintVHDLCode(VHDLFile vhdlFile);
