public void SetAll(StdLogic value)
{
for (int i = 0; i < vector.Length; i++)
{
this.vector[i] = value;
}
}
internal static StdLogic StdLogicXor(StdLogic a, StdLogic b)
{
if (a == StdLogic.X || b == StdLogic.X)
{
return(StdLogic.X);
}
else if (a == StdLogic._0 && b == StdLogic._0)
{
return(StdLogic._0);
}
else if (a == StdLogic._1 && b == StdLogic._1)
{
return(StdLogic._1);
}
else if (a == StdLogic._1 && b == StdLogic._0)
{
return(StdLogic._1);
}
else if (a == StdLogic._0 && b == StdLogic._1)
{
return(StdLogic._1);
}
else
{
// both are Z.
return(StdLogic.Z);
}
}
public override object Evaluate(ParseTreeNode node)
{
if (node.ChildNodes[0].ChildNodes.Count == 1)
{
return(EvaluateGeneral(node.ChildNodes[0].ChildNodes[0]));
}
else
{
var inputSignals = new List <ISignal>();
foreach (var factorNode in node.ChildNodes[0].ChildNodes)
{
var factor = EvaluateGeneral(factorNode);
if (!(factor is ISignal))
{
throw new Exception("unsupported operation");
}
inputSignals.Add((ISignal)factor);
}
var gateType = (LogicGate.GateType)Enum.Parse(typeof(LogicGate.GateType),
node.ChildNodes[0].Term.Name.Split('_')[0], true);
var newSignalName = this.declaredObjects.signalNameGenerator.getSignalName();
var newSignal = new StdLogic(newSignalName);
this.declaredObjects.signalTable[newSignalName] = newSignal;
var logicGate = new LogicGate(gateType, inputSignals, newSignal);
this.declaredObjects.logicGates.Add(logicGate);
return(newSignal);
}
}
public StdLogicVector(int length, StdLogic defaultValue)
{
this.vector = new StdLogic[length];
for (int i = 0; i < length; i++)
{
this.vector[i] = defaultValue;
}
}
public StdLogicVector(StdLogic[] values)
{
this.vector = new StdLogic[values.Length];
for (int i = 0; i < values.Length; i++)
{
this.vector[i] = values[i];
}
}
public StdLogicVector Flip()
{
StdLogic[] vectorFlipped = new StdLogic[vector.Length];
for (int i = 0; i < vector.Length; i++)
{
vectorFlipped[i] = vector[vector.Length - i - 1];
}
return(new StdLogicVector(vectorFlipped));
}
/// <summary>
/// Converts a binary encoding, given as an StdLogicVector with respect to a floating point format to its
/// double representation.
/// </summary>
/// <param name="slv">The binary encoding</param>
/// <param name="fmt">The floating point format to be assumed</param>
/// <returns>The double representation</returns>
public static double ToFloat(this StdLogicVector slv, FloatFormat fmt)
{
if (slv.Size != fmt.TotalWidth)
{
throw new ArgumentException("Vector does not match specified floating point format");
}
slv = slv.ProperValue;
StdLogicVector mantissa = slv[fmt.FractionWidth - 1, 0];
StdLogicVector exponent = slv[fmt.FractionWidth + fmt.ExponentWidth - 1, fmt.FractionWidth];
StdLogic sign = slv[fmt.FractionWidth + fmt.ExponentWidth];
int exp = (int)exponent.ULongValue - fmt.Bias;
if (exponent.Equals(StdLogicVector._0s(fmt.ExponentWidth)))
{
// denormalized
long mant = mantissa.LongValue;
double result = (double)mant * Math.Pow(2.0, exp - 1);
return(result);
}
else if (exponent.Equals(StdLogicVector._1s(fmt.ExponentWidth)))
{
// Infinity / NaN
if (mantissa.Equals(StdLogicVector._0s(fmt.FractionWidth)))
{
// infinity
if (sign == '1')
{
return(double.NegativeInfinity);
}
else
{
return(double.PositiveInfinity);
}
}
else
{
// NaN
return(double.NaN);
}
}
else
{
// normalized
StdLogicVector number = StdLogicVector._1s(1).Concat(mantissa);
ulong mant = number.ULongValue;
double result = (double)mant * Math.Pow(2.0, exp - fmt.FractionWidth);
if (sign == '1')
{
result = -result;
}
return(result);
}
}
internal static StdLogic StdLogicNot(StdLogic a)
{
if (a == StdLogic._0)
{
return(StdLogic._1);
}
else if (a == StdLogic._1)
{
return(StdLogic._0);
}
else
{
return(a);
}
}
/// <summary>
/// Replaces the data symbol of a value-flow with the specified symbol.
/// If the old data symbol is a logic vector, the specified symbol is replicated to a vector.
/// </summary>
/// <param name="vflow">a value-flow</param>
/// <param name="symbol">replacement symbol</param>
/// <returns>new value-flow - same target, but different data symbol</returns>
public static ValueFlow AsDontCareFlow(ValueFlow vflow, StdLogic symbol)
{
StdLogicVector?slvdata = vflow.Value as StdLogicVector?;
StdLogic? sldata = vflow.Value as StdLogic?;
if (slvdata.HasValue)
{
return(new ValueFlow(StdLogicVector.AllSame(symbol, slvdata.Value.Size), vflow.Target));
}
if (sldata.HasValue)
{
return(new ValueFlow(symbol, vflow.Target));
}
return(new ValueFlow(StdLogicVector.AllSame(symbol, Marshal.SerializeForHW(vflow.Value).Size), vflow.Target));
}
// チップのconst_assignを処理
void ProcesConstAssign(
NetComponents libParts,
DeclaredObjectContainer design,
Dictionary <StdLogic, Net> representingNet)
{
foreach (var constAssign in chip.constAssignMappings)
{
Net assignedNet;
if (constAssign.Value.baseName.ToLower() == "open")
{
var tempSignal = new StdLogic(design.signalNameGenerator.getSignalName());
assignedNet = representingNet[tempSignal] = new Net(".temp");
}
else
{
var assignedSignalName = constAssign.Value;
if (!design.signalTable.ContainsKey(assignedSignalName.baseName))
{
throw new CompilerException(
string.Format(@"Signal ""{0}"", which is specified in component ""{1}"" is not defined in the design file",
assignedSignalName.baseName, chip.chipName));
}
var assignedSignal = design.signalTable[assignedSignalName];
if (!(assignedSignal is StdLogic))
{
throw new CompilerException(
string.Format(@"Signal ""{0}"", which is specified in component ""{1}"" is not std_logic",
assignedSignalName.baseName, chip.chipName));
}
assignedNet = representingNet[(StdLogic)assignedSignal];
}
if (!constAssign.Key.attribute.ContainsKey("pin_assign"))
{
throw new CompilerException(
string.Format(@"Port signal ""{0}"" of chip ""{1}"" does not have attribute ""pin_assignment""",
constAssign.Key.name, chip.chipName));
}
int portPin = (int)constAssign.Key.attribute["pin_assign"];
assignedNet.adjacentNodes.Add(new Node(libParts, portPin));
}
}
private void Process()
{
StdLogic ib1 = X.Cur[FracWidth + 1];
StdLogic ib0 = X.Cur[FracWidth];
StdLogicVector rv = X.Cur[FracWidth - 1, 0];
bool ibf1 = ib1 == '1';
bool ibf0 = ib0 == '1';
bool rvz = rv == _zeroes;
bool flag = ibf0 && (ibf1 || !rvz);
if (flag)
{
R.Next = _padOnes.Concat(ib0.Concat(rv));
}
else
{
R.Next = _padZeroes.Concat(ib0.Concat(rv));
}
}
public static String StdLogicToString(StdLogic value)
{
switch (value)
{
case StdLogic._0:
return("0");
case StdLogic._1:
return("1");
case StdLogic.Z:
return("Z");
case StdLogic.X:
return("X");
case StdLogic.U:
return("U");
default:
return(null);
}
}
public StdLogicVector(int length, StdLogic defaultValue)
{
this.vector = new StdLogic[length];
for (int i = 0; i < length; i++)
{
this.vector[i] = defaultValue;
}
}
public override object Evaluate(ParseTreeNode node)
{
if (node.ChildNodes[0].Term.Name == "not")
{
var primary = EvaluateGeneral(node.ChildNodes[1]);
if (!(primary is ISignal))
{
throw new Exception("unsupported operation");
}
var inputSignal = (ISignal)primary;
if (!inputSignal.name.isTemp)
{
// notゲートを生成
var newSignalName = this.declaredObjects.signalNameGenerator.getSignalName();
var newSignal = new StdLogic(newSignalName);
this.declaredObjects.signalTable[newSignalName] = newSignal;
var notGate = new LogicGate(LogicGate.GateType.NOT, new List <ISignal> {
inputSignal
}, newSignal);
this.declaredObjects.logicGates.Add(notGate);
return(newSignal);
}
else
{
// and, or, xorをnand, nor, xnorに変換
foreach (var gate in this.declaredObjects.logicGates)
{
if (gate.outputSignal.Equals(inputSignal))
{
switch (gate.gateType)
{
case LogicGate.GateType.AND:
gate.gateType = LogicGate.GateType.NAND;
break;
case LogicGate.GateType.OR:
gate.gateType = LogicGate.GateType.NOR;
break;
case LogicGate.GateType.XOR:
gate.gateType = LogicGate.GateType.XNOR;
break;
default:
throw new Exception("");
}
return(inputSignal);
}
}
throw new Exception("");
}
}
else
{
return(EvaluateGeneral(node.ChildNodes[0]));
}
}
public StdLogicVector Flip()
{
StdLogic[] vectorFlipped = new StdLogic[vector.Length];
for (int i = 0; i < vector.Length; i++)
{
vectorFlipped[i] = vector[vector.Length-i-1];
}
return new StdLogicVector(vectorFlipped);
}
public void SetAll(StdLogic value)
{
for (int i = 0; i < vector.Length; i++)
{
this.vector[i] = value;
}
}
internal static StdLogic StdLogicNot(StdLogic a)
{
if (a == StdLogic._0)
{
return StdLogic._1;
}
else if (a == StdLogic._1)
{
return StdLogic._0;
}
else
{
return a;
}
}
internal static StdLogic StdLogicXor(StdLogic a, StdLogic b)
{
if (a == StdLogic.X || b == StdLogic.X)
{
return StdLogic.X;
}
else if (a == StdLogic._0 && b == StdLogic._0)
{
return StdLogic._0;
}
else if (a == StdLogic._1 && b == StdLogic._1)
{
return StdLogic._1;
}
else if (a == StdLogic._1 && b == StdLogic._0)
{
return StdLogic._1;
}
else if (a == StdLogic._0 && b == StdLogic._1)
{
return StdLogic._1;
}
else
{
// both are Z.
return StdLogic.Z;
}
}
public override StdLogicVector ConvertValueToWireType(object value)
{
StdLogic sl = (StdLogic)value;
return(StdLogicVector.FromStdLogic(sl));
}
public static String StdLogicToString(StdLogic value)
{
switch (value)
{
case StdLogic._0:
return "0";
case StdLogic._1:
return "1";
case StdLogic.Z:
return "Z";
case StdLogic.X:
return "X";
case StdLogic.U:
return "U";
default:
return null;
}
}
public void Compile(DeclaredObjectContainer design, List <IChipDefinition> chips)
{
this.representingNet = new Dictionary <StdLogic, Net>();
this.resComponentCount = new Dictionary <IChipDefinition, int>();
foreach (ISignal signal in design.signalTable.Values)
{
if (signal is StdLogic)
{
this.representingNet[(StdLogic)signal] = new Net(signal.name.ToString());
}
else if (signal is StdLogicVector)
{
var vector = (StdLogicVector)signal;
for (int i = 0; i < vector.size; ++i)
{
var stdLogic = vector.GetLogic(vector.stRange + i);
this.representingNet[stdLogic] = new Net(stdLogic.name.ToString());
}
}
}
// 代入されたネットの統一
foreach (var assignment in design.assignments)
{
if (assignment.Key is StdLogic && assignment.Value is StdLogic)
{
this.representingNet[(StdLogic)assignment.Key] = this.representingNet[(StdLogic)assignment.Value];
}
else if (assignment.Key is StdLogicVector && assignment.Value is StdLogicVector)
{
var leftVector = (StdLogicVector)assignment.Key;
var rightVector = (StdLogicVector)assignment.Value;
if (leftVector.size != rightVector.size)
{
throw new Exception();
}
for (int i = 0; i < leftVector.size; ++i)
{
this.representingNet[leftVector.GetLogic(leftVector.stRange + i)] =
this.representingNet[rightVector.GetLogic(rightVector.stRange + i)];
}
}
else
{
throw new Exception();
}
}
// 使用されている全てのチップが宣言されているか
var componentChips = new Dictionary <ComponentPrototype, ComponentChipDefinition>();
var gateChips = new Dictionary <LogicGate.GateType, SortedDictionary <int, GateChipDefinition> >();
foreach (var chipDeclaration in chips)
{
if (chipDeclaration is ComponentChipDefinition)
{
componentChips[((ComponentChipDefinition)chipDeclaration).componentPrototype] = (ComponentChipDefinition)chipDeclaration;
}
else if (chipDeclaration is GateChipDefinition)
{
var gateChipDefinition = (GateChipDefinition)chipDeclaration;
if (!gateChips.ContainsKey(gateChipDefinition.gateType))
{
gateChips[gateChipDefinition.gateType] = new SortedDictionary <int, GateChipDefinition>();
}
gateChips[gateChipDefinition.gateType][gateChipDefinition.gateWidth] = gateChipDefinition;
}
}
foreach (var component in design.components)
{
if (!componentChips.ContainsKey(component.prototype))
{
throw new CompilerException(
string.Format(@"No component chip definition was found for component ""{0}""", component.prototype.name));
}
}
foreach (var gate in design.logicGates)
{
if (!gateChips.ContainsKey(gate.gateType))
{
throw new CompilerException(
string.Format(@"No gate chip definition was found for gate ""{0}""", gate.gateType));
}
}
// 回路パーツに変換
this.netComponents = new List <NetComponents>();
var componentQueue = new Dictionary <ComponentPrototype, List <Component> >();
var gateQueue = new Dictionary <LogicGate.GateType, List <LogicGate> >();
foreach (var component in design.components)
{
if (!componentQueue.ContainsKey(component.prototype))
{
componentQueue[component.prototype] = new List <Component>();
}
componentQueue[component.prototype].Add(component);
}
foreach (var gate in design.logicGates)
{
if (!gateQueue.ContainsKey(gate.gateType))
{
gateQueue[gate.gateType] = new List <LogicGate>();
}
gateQueue[gate.gateType].Add(gate);
}
// GNDを取得
if (!design.signalTable.ContainsKey("GND") || !(design.signalTable["GND"] is StdLogic))
{
throw new CompilerException(
string.Format(@"Signal ""{0}"" was not found in design", "GND"));
}
var groundSignal = (StdLogic)design.signalTable["GND"];
// コンポーネントのチップを作成
foreach (var componentPrototype in componentQueue.Keys)
{
// コンポネントの名前で降順ソート
componentQueue[componentPrototype].Sort((x, y) =>
(new ComponentNameComparer()).Compare(y.name, x.name));
while (componentQueue[componentPrototype].Count > 0)
{
int dequeueCount = Math.Min(componentQueue[componentPrototype].Count, componentChips[componentPrototype].componentCount);
var components = new List <Component>();
for (int i = 0; i < dequeueCount; ++i)
{
components.Add(componentQueue[componentPrototype].Last());
componentQueue[componentPrototype].RemoveAt(componentQueue[componentPrototype].Count - 1);
}
this.resComponentCount[componentChips[componentPrototype]] = componentChips[componentPrototype].componentCount - dequeueCount;
// 余ったコンポネントの入力ポートをGNDに固定，出力ポートに仮の信号を接続
for (int i = dequeueCount; i < componentChips[componentPrototype].componentCount; ++i)
{
var portMap = new Dictionary <ISignal, ISignal>();
foreach (var portSignal in componentPrototype.signals)
{
if (portSignal.Value.mode == SignalMode.IN)
{
portMap[portSignal.Value] = groundSignal;
}
else if (portSignal.Value.mode == SignalMode.OUT || portSignal.Value.mode == SignalMode.INOUT)
{
var tempSignal = new StdLogic(design.signalNameGenerator.getSignalName());
this.representingNet[tempSignal] = new Net(".temp");
portMap[portSignal.Value] = tempSignal;
}
}
components.Add(new Component("dummy", componentPrototype, portMap));
}
var parts = new NetComponents(componentChips[componentPrototype], components, this.representingNet, design, this.representingNet);
this.netComponents.Add(parts);
}
}
// ゲートのチップを作成
foreach (var gateType in gateQueue.Keys)
{
int gateWidth = 0;
var gatePool = new List <LogicGate>();
gateQueue[gateType].Sort((x, y) => y.inputSignals.Count - x.inputSignals.Count);
foreach (var gate in gateQueue[gateType])
{
if (gatePool.Count == 0)
{
var gateWidthCandidate = gateChips[gateType].Keys.Where(x => x >= gate.inputSignals.Count);
if (gateWidthCandidate.Count() == 0)
{
throw new CompilerException(
string.Format(@"Gate {0}{1} is not defined", gateType, gate.inputSignals.Count));
}
gateWidth = gateWidthCandidate.First();
}
gatePool.Add(gate);
if (gatePool.Count == gateChips[gateType][gateWidth].gateCount)
{
this.resComponentCount[gateChips[gateType][gateWidth]] = 0;
var parts = new NetComponents(gateChips[gateType][gateWidth], gatePool, this.representingNet, design, this.representingNet);
this.netComponents.Add(parts);
gatePool.Clear();
}
}
if (gatePool.Count > 0)
{
// 余ったゲートの入力をGNDに固定，出力に仮の信号を接続したゲートを追加
var groundSignals = new List <ISignal>();
for (int i = 0; i < gateWidth; ++i)
{
groundSignals.Add(groundSignal);
}
this.resComponentCount[gateChips[gateType][gateWidth]] = gateChips[gateType][gateWidth].gateCount - gatePool.Count;
for (int i = gatePool.Count; i < gateChips[gateType][gateWidth].gateCount; ++i)
{
var tempSignal = new StdLogic(design.signalNameGenerator.getSignalName());
this.representingNet[tempSignal] = new Net(".temp");
gatePool.Add(new LogicGate(gateType, groundSignals, tempSignal));
}
var parts = new NetComponents(gateChips[gateType][gateWidth], gatePool, this.representingNet, design, this.representingNet);
this.netComponents.Add(parts);
}
}
}
public static string ValueOf(StdLogic value)
{
return("sc_logic('" + value.ToString() + "')");
}
/// <summary>
/// Replaces the data symbol of a value-flow with the specified symbol.
/// If the old data symbol is a logic vector, the specified symbol is replicated to a vector.
/// </summary>
/// <param name="vflow">a value-flow</param>
/// <param name="symbol">replacement symbol</param>
/// <returns>new value-flow - same target, but different data symbol</returns>
public static ValueFlow AsDontCareFlow(ValueFlow vflow, StdLogic symbol)
{
StdLogicVector? slvdata = vflow.Value as StdLogicVector?;
StdLogic? sldata = vflow.Value as StdLogic?;
if (slvdata.HasValue)
return new ValueFlow(StdLogicVector.AllSame(symbol, slvdata.Value.Size), vflow.Target);
if (sldata.HasValue)
return new ValueFlow(symbol, vflow.Target);
return new ValueFlow(StdLogicVector.AllSame(symbol, Marshal.SerializeForHW(vflow.Value).Size), vflow.Target);
}
