private void ApplyMicroarchitecture65Nm() { Microarchitecture = MicroArchitecture.Core; switch (Stepping) { case 0x06: // B2 if (CoreCount == 2) { _tjMax = FillCoresFloats(80 + 10); break; } if (CoreCount == 4) { _tjMax = FillCoresFloats(90 + 10); break; } _tjMax = FillCoresFloats(85 + 10); break; case 0x0B: // G0 _tjMax = FillCoresFloats(90 + 10); break; case 0x0D: // M0 _tjMax = FillCoresFloats(85 + 10); break; default: _tjMax = FillCoresFloats(85 + 10); break; } }
private void ApplyMicroarchitecture45NmAtom() { Microarchitecture = MicroArchitecture.Atom; switch (Stepping) { case 0x0A: // A0, B0 _tjMax = FillCoresFloats(100); break; case 0x02: // C0 default: _tjMax = FillCoresFloats(90); break; } }
public IntelCpu(int processorIndex, CpuId[][] cpuId, ISettings settings) : base(processorIndex, cpuId, settings) { // set tjMax float[] tjMax; switch (_family) { case 0x06: { switch (_model) { case 0x0F: // Intel Core 2 (65nm) _microArchitecture = MicroArchitecture.Core; switch (_stepping) { case 0x06: // B2 switch (_coreCount) { case 2: tjMax = Floats(80 + 10); break; case 4: tjMax = Floats(90 + 10); break; default: tjMax = Floats(85 + 10); break; } break; case 0x0B: // G0 tjMax = Floats(90 + 10); break; case 0x0D: // M0 tjMax = Floats(85 + 10); break; default: tjMax = Floats(85 + 10); break; } break; case 0x17: // Intel Core 2 (45nm) _microArchitecture = MicroArchitecture.Core; tjMax = Floats(100); break; case 0x1C: // Intel Atom (45nm) _microArchitecture = MicroArchitecture.Atom; switch (_stepping) { case 0x02: // C0 tjMax = Floats(90); break; case 0x0A: // A0, B0 tjMax = Floats(100); break; default: tjMax = Floats(90); break; } break; case 0x1A: // Intel Core i7 LGA1366 (45nm) case 0x1E: // Intel Core i5, i7 LGA1156 (45nm) case 0x1F: // Intel Core i5, i7 case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm) case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core case 0x2E: // Intel Xeon Processor 7500 series (45nm) case 0x2F: // Intel Xeon Processor (32nm) _microArchitecture = MicroArchitecture.Nehalem; tjMax = GetTjMaxFromMsr(); break; case 0x2A: // Intel Core i5, i7 2xxx LGA1155 (32nm) case 0x2D: // Next Generation Intel Xeon, i7 3xxx LGA2011 (32nm) _microArchitecture = MicroArchitecture.SandyBridge; tjMax = GetTjMaxFromMsr(); break; case 0x3A: // Intel Core i5, i7 3xxx LGA1155 (22nm) case 0x3E: // Intel Core i7 4xxx LGA2011 (22nm) _microArchitecture = MicroArchitecture.IvyBridge; tjMax = GetTjMaxFromMsr(); break; case 0x3C: // Intel Core i5, i7 4xxx LGA1150 (22nm) case 0x3F: // Intel Xeon E5-2600/1600 v3, Core i7-59xx // LGA2011-v3, Haswell-E (22nm) case 0x45: // Intel Core i5, i7 4xxxU (22nm) case 0x46: _microArchitecture = MicroArchitecture.Haswell; tjMax = GetTjMaxFromMsr(); break; case 0x3D: // Intel Core M-5xxx (14nm) case 0x47: // Intel i5, i7 5xxx, Xeon E3-1200 v4 (14nm) case 0x4F: // Intel Xeon E5-26xx v4 case 0x56: // Intel Xeon D-15xx _microArchitecture = MicroArchitecture.Broadwell; tjMax = GetTjMaxFromMsr(); break; case 0x36: // Intel Atom S1xxx, D2xxx, N2xxx (32nm) _microArchitecture = MicroArchitecture.Atom; tjMax = GetTjMaxFromMsr(); break; case 0x37: // Intel Atom E3xxx, Z3xxx (22nm) case 0x4A: case 0x4D: // Intel Atom C2xxx (22nm) case 0x5A: case 0x5D: _microArchitecture = MicroArchitecture.Silvermont; tjMax = GetTjMaxFromMsr(); break; case 0x4E: case 0x5E: // Intel Core i5, i7 6xxxx LGA1151 (14nm) case 0x55: // Intel Core X i7, i9 7xxx LGA2066 (14nm) _microArchitecture = MicroArchitecture.Skylake; tjMax = GetTjMaxFromMsr(); break; case 0x4C: _microArchitecture = MicroArchitecture.Airmont; tjMax = GetTjMaxFromMsr(); break; case 0x8E: case 0x9E: // Intel Core i5, i7 7xxxx (14nm) _microArchitecture = MicroArchitecture.KabyLake; tjMax = GetTjMaxFromMsr(); break; case 0x5C: // Intel ApolloLake _microArchitecture = MicroArchitecture.ApolloLake; tjMax = GetTjMaxFromMsr(); break; case 0xAE: // Intel Core i5, i7 8xxxx (14nm++) _microArchitecture = MicroArchitecture.CoffeeLake; tjMax = GetTjMaxFromMsr(); break; default: _microArchitecture = MicroArchitecture.Unknown; tjMax = Floats(100); break; } } break; case 0x0F: { switch (_model) { case 0x00: // Pentium 4 (180nm) case 0x01: // Pentium 4 (130nm) case 0x02: // Pentium 4 (130nm) case 0x03: // Pentium 4, Celeron D (90nm) case 0x04: // Pentium 4, Pentium D, Celeron D (90nm) case 0x06: // Pentium 4, Pentium D, Celeron D (65nm) _microArchitecture = MicroArchitecture.NetBurst; tjMax = Floats(100); break; default: _microArchitecture = MicroArchitecture.Unknown; tjMax = Floats(100); break; } } break; default: _microArchitecture = MicroArchitecture.Unknown; tjMax = Floats(100); break; } // set timeStampCounterMultiplier switch (_microArchitecture) { case MicroArchitecture.NetBurst: case MicroArchitecture.Atom: case MicroArchitecture.Core: { if (Ring0.ReadMsr(IA32_PERF_STATUS, out uint _, out uint edx)) { _timeStampCounterMultiplier = ((edx >> 8) & 0x1f) + 0.5 * ((edx >> 14) & 1); } } break; case MicroArchitecture.Nehalem: case MicroArchitecture.SandyBridge: case MicroArchitecture.IvyBridge: case MicroArchitecture.Haswell: case MicroArchitecture.Broadwell: case MicroArchitecture.Silvermont: case MicroArchitecture.Skylake: case MicroArchitecture.Airmont: case MicroArchitecture.ApolloLake: case MicroArchitecture.KabyLake: case MicroArchitecture.CoffeeLake: { if (Ring0.ReadMsr(MSR_PLATFORM_INFO, out uint eax, out uint _)) { _timeStampCounterMultiplier = (eax >> 8) & 0xff; } } break; default: _timeStampCounterMultiplier = 0; break; } int coreSensorId = 0; // check if processor supports a digital thermal sensor at core level if (cpuId[0][0].Data.GetLength(0) > 6 && (cpuId[0][0].Data[6, 0] & 1) != 0 && _microArchitecture != MicroArchitecture.Unknown) { _coreTemperatures = new Sensor[_coreCount]; for (int i = 0; i < _coreTemperatures.Length; i++) { _coreTemperatures[i] = new Sensor(CoreString(i), coreSensorId, SensorType.Temperature, this, new[] { new ParameterDescription("TjMax [°C]", "TjMax temperature of the core sensor.\n" + "Temperature = TjMax - TSlope * Value.", tjMax[i]), new ParameterDescription("TSlope [°C]", "Temperature slope of the digital thermal sensor.\n" + "Temperature = TjMax - TSlope * Value.", 1) }, settings); ActivateSensor(_coreTemperatures[i]); coreSensorId++; } } else { _coreTemperatures = new Sensor[0]; } // check if processor supports a digital thermal sensor at package level if (cpuId[0][0].Data.GetLength(0) > 6 && (cpuId[0][0].Data[6, 0] & 0x40) != 0 && _microArchitecture != MicroArchitecture.Unknown) { _packageTemperature = new Sensor("CPU Package", coreSensorId, SensorType.Temperature, this, new[] { new ParameterDescription("TjMax [°C]", "TjMax temperature of the package sensor.\n" + "Temperature = TjMax - TSlope * Value.", tjMax[0]), new ParameterDescription("TSlope [°C]", "Temperature slope of the digital thermal sensor.\n" + "Temperature = TjMax - TSlope * Value.", 1) }, settings); ActivateSensor(_packageTemperature); coreSensorId++; } // dist to tjmax sensor if (cpuId[0][0].Data.GetLength(0) > 6 && (cpuId[0][0].Data[6, 0] & 1) != 0 && _microArchitecture != MicroArchitecture.Unknown) { _distToTjMaxTemperatures = new Sensor[_coreCount]; for (int i = 0; i < _distToTjMaxTemperatures.Length; i++) { _distToTjMaxTemperatures[i] = new Sensor(CoreString(i) + " Distance to TjMax", coreSensorId, SensorType.Temperature, this, settings); ActivateSensor(_distToTjMaxTemperatures[i]); coreSensorId++; } } else { _distToTjMaxTemperatures = new Sensor[0]; } //core temp avg and max value //is only available when the cpu has more than 1 core if (cpuId[0][0].Data.GetLength(0) > 6 && (cpuId[0][0].Data[6, 0] & 0x40) != 0 && _microArchitecture != MicroArchitecture.Unknown && _coreCount > 1) { _coreMax = new Sensor("Core Max", coreSensorId, SensorType.Temperature, this, settings); ActivateSensor(_coreMax); coreSensorId++; _coreAvg = new Sensor("Core Average", coreSensorId, SensorType.Temperature, this, settings); ActivateSensor(_coreAvg); } else { _coreMax = null; _coreAvg = null; } _busClock = new Sensor("Bus Speed", 0, SensorType.Clock, this, settings); _coreClocks = new Sensor[_coreCount]; for (int i = 0; i < _coreClocks.Length; i++) { _coreClocks[i] = new Sensor(CoreString(i), i + 1, SensorType.Clock, this, settings); if (HasTimeStampCounter && _microArchitecture != MicroArchitecture.Unknown) { ActivateSensor(_coreClocks[i]); } } if (_microArchitecture == MicroArchitecture.SandyBridge || _microArchitecture == MicroArchitecture.IvyBridge || _microArchitecture == MicroArchitecture.Haswell || _microArchitecture == MicroArchitecture.Broadwell || _microArchitecture == MicroArchitecture.Skylake || _microArchitecture == MicroArchitecture.Silvermont || _microArchitecture == MicroArchitecture.Airmont || _microArchitecture == MicroArchitecture.KabyLake || _microArchitecture == MicroArchitecture.ApolloLake) { _powerSensors = new Sensor[_energyStatusMsrs.Length]; _lastEnergyTime = new DateTime[_energyStatusMsrs.Length]; _lastEnergyConsumed = new uint[_energyStatusMsrs.Length]; if (Ring0.ReadMsr(MSR_RAPL_POWER_UNIT, out uint eax, out uint _)) { switch (_microArchitecture) { case MicroArchitecture.Silvermont: case MicroArchitecture.Airmont: _energyUnitMultiplier = 1.0e-6f * (1 << (int)((eax >> 8) & 0x1F)); break; default: _energyUnitMultiplier = 1.0f / (1 << (int)((eax >> 8) & 0x1F)); break; } } if (_energyUnitMultiplier != 0) { for (int i = 0; i < _energyStatusMsrs.Length; i++) { if (!Ring0.ReadMsr(_energyStatusMsrs[i], out eax, out uint _)) { continue; } _lastEnergyTime[i] = DateTime.UtcNow; _lastEnergyConsumed[i] = eax; _powerSensors[i] = new Sensor(_powerSensorLabels[i], i, SensorType.Power, this, settings); ActivateSensor(_powerSensors[i]); } } } Update(); }
private void DetectMicroarchitecture() { // https://en.wikichip.org/wiki/intel/microarchitectures switch (Family) { case 0x06: { switch (ModelId) { // Intel Core 2 (65nm) case 0x0F: ApplyMicroarchitecture65Nm(); break; // Intel Core 2 (45nm) case 0x17: ApplyMicroarchitecture45Nm(); break; // Intel Atom (45nm) case 0x1C: ApplyMicroarchitecture45NmAtom(); break; case 0x1A: // Intel Core i7 LGA1366 (45nm) case 0x1E: // Intel Core i5, i7 LGA1156 (45nm) case 0x1F: // Intel Core i5, i7 case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm) case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core case 0x2E: // Intel Xeon Processor 7500 series (45nm) case 0x2F: // Intel Xeon Processor (32nm) Microarchitecture = MicroArchitecture.Nehalem; _tjMax = GetTjMaxFromMsr(); break; case 0x2A: // Intel Core i5, i7 2xxx LGA1155 (32nm) case 0x2D: // Next Generation Intel Xeon, i7 3xxx LGA2011 (32nm) Microarchitecture = MicroArchitecture.SandyBridge; _tjMax = GetTjMaxFromMsr(); break; case 0x3A: // Intel Core i5, i7 3xxx LGA1155 (22nm) case 0x3E: // Intel Core i7 4xxx LGA2011 (22nm) Microarchitecture = MicroArchitecture.IvyBridge; _tjMax = GetTjMaxFromMsr(); break; case 0x3C: // Intel Core i5, i7 4xxx LGA1150 (22nm) case 0x3F: // Intel Xeon E5-2600/1600 v3, Core i7-59xx // LGA2011-v3, Haswell-E (22nm) case 0x45: // Intel Core i5, i7 4xxxU (22nm) case 0x46: Microarchitecture = MicroArchitecture.Haswell; _tjMax = GetTjMaxFromMsr(); break; case 0x3D: // Intel Core M-5xxx (14nm) case 0x47: // Intel i5, i7 5xxx, Xeon E3-1200 v4 (14nm) case 0x4F: // Intel Xeon E5-26xx v4 case 0x56: // Intel Xeon D-15xx Microarchitecture = MicroArchitecture.Broadwell; _tjMax = GetTjMaxFromMsr(); break; case 0x36: // Intel Atom S1xxx, D2xxx, N2xxx (32nm) Microarchitecture = MicroArchitecture.Atom; _tjMax = GetTjMaxFromMsr(); break; case 0x37: // Intel Atom E3xxx, Z3xxx (22nm) case 0x4A: case 0x4D: // Intel Atom C2xxx (22nm) case 0x5A: case 0x5D: Microarchitecture = MicroArchitecture.Silvermont; _tjMax = GetTjMaxFromMsr(); break; case 0x4E: case 0x5E: // Intel Core i5, i7 6xxxx LGA1151 (14nm) Microarchitecture = MicroArchitecture.Skylake; _tjMax = GetTjMaxFromMsr(); break; case 0x4C: Microarchitecture = MicroArchitecture.Airmont; _tjMax = GetTjMaxFromMsr(); break; case 0x8E: // Intel Core i5, i7 7xxxx (14nm) Microarchitecture = MicroArchitecture.KabyLake; _tjMax = GetTjMaxFromMsr(); break; case 0x9E: // Intel Core i3, i5, i7, i9 (14nm) Microarchitecture = MicroArchitecture.CoffeeLake; _tjMax = GetTjMaxFromMsr(); break; default: Microarchitecture = MicroArchitecture.Unknown; _tjMax = FillCoresFloats(100); break; } break; } case 0x0F: { switch (ModelId) { case 0x00: // Pentium 4 (180nm) case 0x01: // Pentium 4 (130nm) case 0x02: // Pentium 4 (130nm) case 0x03: // Pentium 4, Celeron D (90nm) case 0x04: // Pentium 4, Pentium D, Celeron D (90nm) case 0x06: // Pentium 4, Pentium D, Celeron D (65nm) Microarchitecture = MicroArchitecture.NetBurst; _tjMax = FillCoresFloats(100); break; default: Microarchitecture = MicroArchitecture.Unknown; _tjMax = FillCoresFloats(100); break; } break; } default: Microarchitecture = MicroArchitecture.Unknown; _tjMax = FillCoresFloats(100); break; } }
private void ApplyMicroarchitecture45Nm() { Microarchitecture = MicroArchitecture.Core; _tjMax = FillCoresFloats(100); }