public byte ReadMemory(ushort addr) { MemoryCallbacks.CallReads(addr, "System Bus"); if (addr < 0x8000) { return(mapper.ReadMemory(addr)); } else if (addr < 0xC800) { return(0xFF); } else if (addr < 0xD000) { return(RAM[(addr - 0xC800) & 0x3FF]); } else if (addr < 0xD800) { return(Read_Registers(addr & 0xF)); } else if (addr < 0xE000) { return(0xFF); } else if (addr < 0xF000) { return(0xFF); } else { return(_bios[addr - 0xF000]); } }
private void InitMemCallbacks() { ExecCallback = new LibGPGX.mem_cb(a => MemoryCallbacks.CallExecutes(a, "M68K BUS")); ReadCallback = new LibGPGX.mem_cb(a => MemoryCallbacks.CallReads(a, "M68K BUS")); WriteCallback = new LibGPGX.mem_cb(a => MemoryCallbacks.CallWrites(a, "M68K BUS")); _memoryCallbacks.ActiveChanged += RefreshMemCallbacks; }
private void ReadHook(uint addr) { MemoryCallbacks.CallReads(addr); // we RefreshMemoryCallbacks() after the trigger in case the trigger turns itself off at that point // EDIT: for now, theres some IPC re-entrancy problem // RefreshMemoryCallbacks(); }
private void SetCallbacks() { _machine.Memory.ReadCallback = (addr) => MemoryCallbacks.CallReads(addr, "System Bus"); _machine.Memory.WriteCallback = (addr) => MemoryCallbacks.CallWrites(addr, "System Bus"); _machine.Memory.ExecuteCallback = (addr) => MemoryCallbacks.CallExecutes(addr, "System Bus"); _machine.Memory.InputCallback = InputCallbacks.Call; }
public byte ReadMemoryWrapper(ushort addr) { if (MemoryCallbacks != null) { MemoryCallbacks.CallReads(addr); } return(ReadMemory(addr)); }
void InitCallbacks() { padcb = new LibVBANext.StandardCallback(() => InputCallbacks.Call()); fetchcb = new LibVBANext.AddressCallback((addr) => MemoryCallbacks.CallExecutes(addr)); readcb = new LibVBANext.AddressCallback((addr) => MemoryCallbacks.CallReads(addr)); writecb = new LibVBANext.AddressCallback((addr) => MemoryCallbacks.CallWrites(addr)); tracecb = new LibVBANext.TraceCallback((addr, opcode) => Tracer.Put(Trace(addr, opcode))); _inputCallbacks.ActiveChanged += SyncPadCallback; _memorycallbacks.ActiveChanged += SyncMemoryCallbacks; }
public byte ReadMemory(ushort addr) { byte ret; if (addr >= 0x8000) { //easy optimization, since rom reads are so common, move this up (reordering the rest of these elseifs is not easy) ret = Board.ReadPRG(addr - 0x8000); } else if (addr < 0x0800) { ret = ram[addr]; } else if (addr < 0x2000) { ret = ram[addr & 0x7FF]; } else if (addr < 0x4000) { ret = Board.ReadReg2xxx(addr); } else if (addr < 0x4020) { ret = ReadReg(addr); //we're not rebasing the register just to keep register names canonical } else if (addr < 0x6000) { ret = Board.ReadEXP(addr - 0x4000); } else { ret = Board.ReadWRAM(addr - 0x6000); } // handle cheats (currently cheats can only freeze read only areas) // there is no way to distinguish between a memory poke and a memory freeze if (num_cheats != 0) { for (int i = 0; i < num_cheats; i++) { if (cheat_indexes[i] == addr) { ret = cheat_active[addr]; } } } MemoryCallbacks.CallReads(addr, "System Bus"); DB = ret; return(ret); }
public byte FetchMemoryWrapper(ushort addr) { if (MemoryCallbacks != null) { MemoryCallbacks.CallReads(addr); } if (FetchMemory != null) { return(FetchMemory(addr, false)); } return(ReadMemory(addr)); }
internal byte ReadMemory(ushort addr) { if (addr != LastAddress) { DistinctAccessCount++; LastAddress = addr; } _mapper.Bit13 = addr.Bit(13); var temp = _mapper.ReadMemory((ushort)(addr & 0x1FFF)); MemoryCallbacks.CallReads(addr); return(temp); }
public byte ReadMemory(ushort addr) { byte ret; if (addr >= 0x8000) { ret = Board.ReadPRG(addr - 0x8000); //easy optimization, since rom reads are so common, move this up (reordering the rest of these elseifs is not easy) } else if (addr < 0x0800) { ret = ram[addr]; } else if (addr < 0x2000) { ret = ram[addr & 0x7FF]; } else if (addr < 0x4000) { ret = Board.ReadReg2xxx(addr); } else if (addr < 0x4020) { ret = ReadReg(addr); //we're not rebasing the register just to keep register names canonical } else if (addr < 0x6000) { ret = Board.ReadEXP(addr - 0x4000); } else { ret = Board.ReadWRAM(addr - 0x6000); } //handle breakpoints and stuff. //the idea is that each core can implement its own watch class on an address which will track all the different kinds of monitors and breakpoints and etc. //but since freeze is a common case, it was implemented through its own mechanisms if (sysbus_watch[addr] != null) { sysbus_watch[addr].Sync(); ret = sysbus_watch[addr].ApplyGameGenie(ret); } MemoryCallbacks.CallReads(addr); DB = ret; return(ret); }
private byte ReadMemory(ushort addr) { if (addr != _lastAddress) { DistinctAccessCount++; _lastAddress = addr; } _mapper.Bit13 = addr.Bit(13); var temp = _mapper.ReadMemory((ushort)(addr & 0x1FFF)); _tia.BusState = temp; MemoryCallbacks.CallReads(addr); return(temp); }
public byte ReadMemory(ushort addr) { MemoryCallbacks.CallReads(addr); if ((addr & 0xFCE0) == 0) { // return TIA registers or control register if it is still unlocked if ((A7800_control_register & 0x1) == 0) { return(0xFF); // TODO: what to return here? } else { return(tia.ReadMemory((ushort)(addr & 0x1F), false)); //return TIA_regs[addr & 0x1F]; // TODO: what to return here? } } else if ((addr & 0xFCE0) == 0x20) { if ((A7800_control_register & 0x2) > 0) { return(Maria_regs[addr & 0x1F]); } else { return(0xFF); // TODO: What if Maria is off? } } else if ((addr & 0xFF80) == 0x280) { //return regs_6532[addr & 0x1F]; return(m6532.ReadMemory(addr, false)); } else if ((addr & 0xFE80) == 0x480) { return(RAM_6532[addr & 0x7F]); } else if ((addr >= 0x1800) && (addr < 0x2800)) { return(RAM[addr - 0x1800]); } else if ((addr >= 0x40) && (addr < 0x100)) { // RAM block 0 return(RAM[addr - 0x40 + 0x840]); } else if ((addr >= 0x140) && (addr < 0x200)) { // RAM block 1 return(RAM[addr - 0x140 + 0x940]); } else if ((addr >= 0x2800) && (addr < 0x3000)) { return(RAM[(addr & 0x7FF) + 0x800]); } else if ((addr >= 0x3000) && (addr < 0x4000)) { // could be either RAM mirror or ROM return(mapper.ReadMemory(addr)); } else if ((addr >= 0x400) && (addr < 0x480)) { // cartridge space available return(mapper.ReadMemory(addr)); } else if ((addr >= 0x500) && (addr < 0x1800)) { // cartridge space available return(mapper.ReadMemory(addr)); } else { return(mapper.ReadMemory(addr)); } }
public byte ReadMemory(ushort addr) { MemoryCallbacks.CallReads(addr, "System Bus"); addr_access = addr; if (ppu.DMA_start) { // some of gekkio's tests require these to be accessible during DMA if (addr < 0x8000) { if (ppu.DMA_addr < 0x80) { return(0xFF); } else { return(mapper.ReadMemory(addr)); } } else if ((addr >= 0xE000) && (addr < 0xF000)) { return(RAM[addr - 0xE000]); } else if ((addr >= 0xF000) && (addr < 0xFE00)) { return(RAM[(RAM_Bank * 0x1000) + (addr - 0xF000)]); } else if ((addr >= 0xFE00) && (addr < 0xFEA0) && ppu.DMA_OAM_access) { return(OAM[addr - 0xFE00]); } else if ((addr >= 0xFF00) && (addr < 0xFF80)) // The game GOAL! Requires Hardware Regs to be accessible { return(Read_Registers(addr)); } else if ((addr >= 0xFF80)) { return(ZP_RAM[addr - 0xFF80]); } return(0xFF); } if (addr < 0x900) { if (addr < 0x100) { // return Either BIOS ROM or Game ROM if ((GB_bios_register & 0x1) == 0) { return(_bios[addr]); // Return BIOS } else { return(mapper.ReadMemory(addr)); } } else if (addr >= 0x200) { // return Either BIOS ROM or Game ROM if (((GB_bios_register & 0x1) == 0) && is_GBC) { return(_bios[addr]); // Return BIOS } else { return(mapper.ReadMemory(addr)); } } else { return(mapper.ReadMemory(addr)); } } else if (addr < 0x8000) { return(mapper.ReadMemory(addr)); } else if (addr < 0xA000) { if (ppu.VRAM_access_read) { return(VRAM[(VRAM_Bank * 0x2000) + (addr - 0x8000)]); } else { return(0xFF); } } else if (addr < 0xC000) { return(mapper.ReadMemory(addr)); } else if (addr < 0xD000) { return(RAM[addr - 0xC000]); } else if (addr < 0xE000) { return(RAM[(RAM_Bank * 0x1000) + (addr - 0xD000)]); } else if (addr < 0xF000) { return(RAM[addr - 0xE000]); } else if (addr < 0xFE00) { return(RAM[(RAM_Bank * 0x1000) + (addr - 0xF000)]); } else if (addr < 0xFEA0) { if (ppu.OAM_access_read) { return(OAM[addr - 0xFE00]); } else { return(0xFF); } } else if (addr < 0xFF00) { // unmapped memory, returns 0xFF return(0xFF); } else if (addr < 0xFF80) { return(Read_Registers(addr)); } else if (addr < 0xFFFF) { return(ZP_RAM[addr - 0xFF80]); } else { return(Read_Registers(addr)); } }
public byte ReadMemory(ushort addr) { MemoryCallbacks.CallReads(addr, "System Bus"); if ((addr & 0xFCE0) == 0) { // return TIA registers or control register if it is still unlocked if ((A7800_control_register & 0x1) == 0) { return(0xFF); // TODO: what to return here? } else { slow_access = true; return(tia.ReadMemory((ushort)(addr & 0x1F), false)); } } else if ((addr & 0xFCE0) == 0x20) { if ((A7800_control_register & 0x2) > 0) { return(Maria_regs[addr & 0x1F]); } else { return(0x80); // TODO: What if Maria is off? } } else if ((addr & 0xFF80) == 0x280) { slow_access = true; return(m6532.ReadMemory(addr, false)); } else if ((addr & 0xFE80) == 0x480) { slow_access = true; return(RAM_6532[addr & 0x7F]); } else if ((addr >= 0x1800) && (addr < 0x2800)) { return(RAM[addr - 0x1800]); } else if ((addr >= 0x40) && (addr < 0x100)) { // RAM block 0 return(RAM[addr - 0x40 + 0x840]); } else if ((addr >= 0x140) && (addr < 0x200)) { // RAM block 1 return(RAM[addr - 0x140 + 0x940]); } else if ((addr >= 0x2800) && (addr < 0x3000)) { // this mirror evidently does not exist on hardware despite being in the documentation return(0xFF); // RAM[(addr & 0x7FF) + 0x800]; } else if ((addr >= 0x3000) && (addr < 0x4000)) { // could be either RAM mirror or ROM return(mapper.ReadMemory(addr)); } else if ((addr >= 0x400) && (addr < 0x480)) { // cartridge space available return(mapper.ReadMemory(addr)); } else if ((addr >= 0x500) && (addr < 0x1800)) { // cartridge space available return(mapper.ReadMemory(addr)); } else { return(mapper.ReadMemory(addr)); } }
void ReadCallback(uint addr) { MemoryCallbacks.CallReads(addr, "System Bus"); }
private byte ReadMemory(ushort addr) { MemoryCallbacks.CallReads(addr, "System Bus"); return(ReadMemoryMapper(addr)); }
void ReadCallback(uint addr) { MemoryCallbacks.CallReads(addr); }
private void ReadHook_SMP(uint addr) { MemoryCallbacks.CallReads(addr, "SMP"); }
public byte ReadMemory(ushort addr) { MemoryCallbacks.CallReads(addr); if (addr < 0x0400) { if ((addr & 0xFF) < 0x20) { // return TIA registers or control register if it is still unlocked if ((A7800_control_register & 0x1) == 0 && (addr < 0x20)) { return(0xFF); // TODO: what to return here? } else { return(TIA_regs[addr]); // TODO: what to return here? } } else if ((addr & 0xFF) < 0x40) { if ((A7800_control_register & 0x2) > 0) { return(Maria_regs[(addr & 0x3F) - 0x20]); } else { return(0xFF); } } else if (addr < 0x100) { // RAM block 0 return(RAM[addr - 0x40 + 0x840]); } else if (addr < 0x200) { // RAM block 1 return(RAM[addr - 0x140 + 0x940]); } else if (addr < 0x300) { return(regs_6532[addr - 0x240]); } else { return(0xFF); // what is mapped here? } } else if (addr < 0x480) { // cartridge space available return(mapper.ReadMemory(addr)); } else if (addr < 0x500) { // this is where RAM for the 6532 resides for use in 2600 mode return(0xFF); } else if (addr < 0x1800) { // cartridge space available return(mapper.ReadMemory(addr)); } else if (addr < 0x2800) { return(RAM[addr - 0x1800]); } else if (addr < 0x4000) { // could be either RAM mirror or ROM return(mapper.ReadMemory(addr)); } else { return(mapper.ReadMemory(addr)); } }