protected void RefreshBank(uint rankIdx, uint bankIdx)
{
List <Req> q = Mctrl.Refbankqs[rankIdx, bankIdx];
Req req = RequestPool.Depool();
req.Type = ReqType.REFRESH_BANK;
req.TsArrival = Cycles;
// Set up the refresh target address
MemAddr addr = new MemAddr();
addr.Reset();
addr.cid = Mctrl.cid;
addr.rid = rankIdx;
addr.bid = bankIdx;
addr.said = SaCountersPerbank[rankIdx, bankIdx];
req.Addr = addr;
q.Add(req);
// Update states
BankCounters[rankIdx]++;
if (BankCounters[rankIdx] == BankCounterMax)
{
BankCounters[rankIdx] = 0;
}
SaCountersPerbank[rankIdx, bankIdx]++;
if (SaCountersPerbank[rankIdx, bankIdx] == SaCounterMax)
{
SaCountersPerbank[rankIdx, bankIdx] = 0;
}
}
private bool insert_mctrl(Req req)
{
MemAddr addr = req.Addr;
//failure
if (Sim.Sim.Mctrls[addr.cid].is_q_full(pid, req.Type, addr.rid, addr.bid))
{
if (req.Type == ReqType.READ)
{
Stat.procs[req.Pid].stall_read_mctrl.collect();
}
else if (req.Type == ReqType.WRITE)
{
Stat.procs[req.Pid].stall_write_mctrl.collect();
}
else if (req.Type == ReqType.COPY)
{
Stat.procs[req.Pid].stall_copy_mctrl.collect();
}
return(false);
}
//success
send_req(req);
return(true);
}
public MemAddr inst_wnd_head_addr()
{
ulong block_addr = inst_wnd.head();
ulong paddr = block_addr << Config.proc.block_size_bits;
MemAddr addr = MemMap.Translate(paddr);
return(addr);
}
// Generate a temporary refresh request that is used for probing the availability of DRAM to issue a refresh
// Giving a bank idx of -1 makes an all-bank refresh request
public virtual Req GenRefreshBankReq(int rankIdx, int bankIdx)
{
Req req = new Req
{
Type = (bankIdx == -1) ? ReqType.REFRESH : ReqType.REFRESH_BANK,
TsArrival = Cycles
};
// Set up the refresh target address
MemAddr addr = new MemAddr();
addr.Reset();
addr.cid = Mctrl.cid;
addr.rid = (uint)rankIdx;
if (bankIdx != -1)
{
addr.bid = (uint)bankIdx;
}
req.Addr = addr;
return(req);
}
public void Set(int pid, ReqType type, ulong paddr)
{
// state
Pid = pid;
Type = type;
// address
TracePaddr = paddr;
if (Config.mctrl.page_randomize)
{
Paddr = Prand.get_paddr(paddr);
}
else if (Config.mctrl.page_sequence)
{
Paddr = Pseq.get_paddr(paddr);
}
else if (Config.mctrl.page_contiguous)
{
Paddr = Pcontig.get_paddr(paddr);
}
else
{
Paddr = paddr;
}
BlockAddr = Paddr >> Config.proc.block_size_bits;
Addr = MemMap.Translate(Paddr);
Stat.procs[pid].allocated_physical_pages.collect();
reset_timing();
// Word offset
ulong pwo = (Paddr & (63)) >> 2;
Dbg.AssertPrint(pwo == ((paddr & (63)) >> 2),
"Word offset should be the same for both virtual and physical addresses.");
Dbg.AssertPrint(pwo < 16, "There should be only 8 words in a cacheline=" + pwo);
WordOffset = (int)pwo;
}
protected void RefreshRank(uint rankIdx)
{
List <Req> q = Mctrl.Refrankqs[rankIdx];
Req req = RequestPool.Depool();
req.Type = ReqType.REFRESH;
req.TsArrival = Cycles;
// Set up the refresh target address
MemAddr addr = new MemAddr();
addr.Reset();
addr.cid = Mctrl.cid;
addr.rid = rankIdx;
addr.said = SaCounters[rankIdx];
req.Addr = addr;
q.Add(req);
SaCounters[rankIdx]++;
if (SaCounters[rankIdx] == SaCounterMax)
{
SaCounters[rankIdx] = 0;
}
}
public Cmd(CmdType type, MemAddr addr, Req req)
{
Addr = addr;
Type = type;
Req = req;
}
public BusTransaction(MemAddr addr, long ts)
{
Addr = addr;
this.ts = ts;
}