private void m_txtManualFilter_KeyUp(object sender, KeyEventArgs e)
{
if (e.KeyCode == Keys.Enter)
{
Regex userFilter = null;
try
{
userFilter = new Regex(m_txtManualFilter.Text);
}
catch (ArgumentException exception)
{
MessageBox.Show(exception.Message, "Error", MessageBoxButtons.OK, MessageBoxIcon.Error);
return;
}
// clear selection and reselect all rows that match the user filter
m_grdViewInstances.ClearSelection();
for (int index = 0; index < LibraryElementInstanceManager.Instance.Instances.Count; index++)
{
LibElemInst instance = LibraryElementInstanceManager.Instance.Instances[index];
if (userFilter.IsMatch(instance.InstanceName))
{
m_grdViewInstances.Rows[index].Selected = true;
}
}
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
LibElemInst inst = LibraryElementInstanceManager.Instance.GetInstantiation(InstanceName);
LibraryElement libElement = Objects.Library.Instance.GetElement(inst.LibraryElementName);
Tile anchorCLB = FPGA.FPGA.Instance.GetTile(inst.AnchorLocation);
NetlistContainer netlistContainer = GetNetlistContainer();
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
RelocateInstancesForXDL(libElement, anchorCLB, (XDLContainer)netlistContainer);
RelocateNetsForXDL(libElement, anchorCLB, (XDLContainer)netlistContainer);
// add design config
if (AddDesignConfig && libElement.Containter is XDLContainer && ((XDLContainer)netlistContainer).GetDesignConfig().Length == 0)
{
((XDLContainer)netlistContainer).AddDesignConfig(((XDLContainer)libElement.Containter).GetDesignConfig());
}
break;
case FPGATypes.BackendType.Vivado:
RelocateInstancesForTCL(libElement, anchorCLB, (TCLContainer)netlistContainer);
RelocateNetsForTCL(libElement, anchorCLB, netlistContainer);
break;
}
}
private void AddISEInstantiation(Tile t)
{
LibElemInst instance = new LibElemInst();
instance.AnchorLocation = t.Location;
instance.InstanceName = GetNextInstanceName();
instance.LibraryElementName = LibraryElementName;
instance.SliceNumber = SliceNumber;
instance.SliceName = t.Slices[(int)SliceNumber].SliceName;
LibraryElementInstanceManager.Instance.Add(instance);
// mark source as blocked
ExcludeInstantiationSourcesFromBlocking markSrc = new ExcludeInstantiationSourcesFromBlocking();
markSrc.AnchorLocation = t.Location;
markSrc.LibraryElementName = LibraryElementName;
CommandExecuter.Instance.Execute(markSrc);
SaveLibraryElementInstantiation saveCmd = new SaveLibraryElementInstantiation();
saveCmd.AddDesignConfig = false;
saveCmd.InsertPrefix = true;
saveCmd.InstanceName = instance.InstanceName;
saveCmd.NetlistContainerName = NetlistContainerName;
CommandExecuter.Instance.Execute(saveCmd);
}
public VHDLInstantiation(VHDLFile container, LibElemInst instantiation, LibraryElement libElement, Command callee)
{
m_container = container;
m_instantation = instantiation;
m_libraryElement = libElement;
IntergrateIntoContainer(callee);
}
protected override void DoCommandAction()
{
LibraryElement libElement = Objects.Library.Instance.GetElement(LibraryElementName);
Tile anchor = FPGA.FPGA.Instance.GetTile(AnchorLocation);
if (libElement.ResourceShape.Anchor.AnchorSliceNumber >= anchor.Slices.Count)
{
throw new ArgumentException("Too few slices on tile " + anchor.Location + ". Expecting " + libElement.ResourceShape.Anchor.AnchorSliceNumber + " but found " + anchor.Slices.Count + " slice.");
}
if (IdentifierManager.Instance.IsMatch(anchor.Location, IdentifierManager.RegexTypes.Interconnect))
{
anchor = FPGATypes.GetCLTile(anchor).FirstOrDefault();
}
if (AutoClearModuleSlot)
{
//this.FastAutoClearModuleSlotBeforeInstantiation(libElement, Enumerable.Repeat(anchor, 1));
AutoClearModuleSlotBeforeInstantiation(libElement, Enumerable.Repeat(anchor, 1));
}
LibElemInst instantiation = new LibElemInst();
instantiation.AnchorLocation = AnchorLocation;
instantiation.InstanceName = Hierarchy + InstanceName;
instantiation.LibraryElementName = LibraryElementName;
instantiation.SliceNumber = libElement.ResourceShape.Anchor.AnchorSliceNumber;
instantiation.SliceName = anchor.Slices[(int)libElement.ResourceShape.Anchor.AnchorSliceNumber].SliceName;
LibraryElementInstanceManager.Instance.Add(instantiation);
// mark source as blocked
ExcludeInstantiationSourcesFromBlocking markSrc = new ExcludeInstantiationSourcesFromBlocking();
markSrc.AnchorLocation = AnchorLocation;
markSrc.LibraryElementName = LibraryElementName;
CommandExecuter.Instance.Execute(markSrc);
SaveLibraryElementInstantiation saveCmd = new SaveLibraryElementInstantiation();
saveCmd.AddDesignConfig = false;
saveCmd.InsertPrefix = true;
saveCmd.InstanceName = InstanceName;
saveCmd.NetlistContainerName = NetlistContainerName;
CommandExecuter.Instance.Execute(saveCmd);
if (AutoFuse)
{
FuseNets fuseCmd = new FuseNets();
fuseCmd.NetlistContainerName = NetlistContainerName;
fuseCmd.Mute = Mute;
fuseCmd.Profile = Profile;
fuseCmd.PrintProgress = PrintProgress;
CommandExecuter.Instance.Execute(fuseCmd);
}
}
protected override void DoCommandAction()
{
CheckParameters();
for (int i = 0; i < NumberOfPrimitives; i++)
{
LibElemInst instance = new LibElemInst();
instance.InstanceName = GetNextInstanceName();
instance.LibraryElementName = LibraryElementName;
LibraryElementInstanceManager.Instance.Add(instance);
}
}
protected override void DoCommandAction()
{
NetlistContainer netlistContainer = GetNetlistContainer();
Slice anchor = FPGA.FPGA.Instance.GetSlice(SliceName);
LibraryElement libElement = Objects.Library.Instance.GetElement(LibraryElementName);
if (anchor == null)
{
throw new ArgumentException("Can not find Slice " + SliceName);
}
if (AutoClearModuleSlot)
{
AutoClearModuleSlotBeforeInstantiation(libElement, Enumerable.Repeat(anchor.ContainingTile, 1));
}
LibElemInst instantiation = new LibElemInst();
instantiation.AnchorLocation = anchor.ContainingTile.Location;
instantiation.InstanceName = Hierarchy + InstanceName;
instantiation.LibraryElementName = LibraryElementName;
instantiation.SliceNumber = anchor.ContainingTile.GetSliceNumberByName(SliceName);
instantiation.SliceName = SliceName;
LibraryElementInstanceManager.Instance.Add(instantiation);
// mark source as blocked
ExcludeInstantiationSourcesFromBlocking markSrc = new ExcludeInstantiationSourcesFromBlocking();
markSrc.AnchorLocation = anchor.ContainingTile.Location;
markSrc.LibraryElementName = LibraryElementName;
CommandExecuter.Instance.Execute(markSrc);
SaveLibraryElementInstantiation saveCmd = new SaveLibraryElementInstantiation();
saveCmd.AddDesignConfig = false;
saveCmd.InsertPrefix = true;
saveCmd.InstanceName = InstanceName;
saveCmd.NetlistContainerName = NetlistContainerName;
CommandExecuter.Instance.Execute(saveCmd);
if (AutoFuse)
{
FuseNets fuseCmd = new FuseNets();
fuseCmd.NetlistContainerName = NetlistContainerName;
fuseCmd.Mute = Mute;
fuseCmd.Profile = Profile;
fuseCmd.PrintProgress = PrintProgress;
CommandExecuter.Instance.Execute(fuseCmd);
}
}
private void AddVivadoInstantiation(Tile t)
{
LibraryElement libElement = Objects.Library.Instance.GetElement(LibraryElementName);
if (libElement.VivadoConnectionPrimitive)
{
// bei Vivado 4 LUT6-Instanzen erstellen, eine mit Inputs und Output, drei davon dann nur mit Output
// only VivaodConnection primitves contains SubElements
bool checkResources = true;
foreach (LibraryElement other in libElement.SubElements)
{
LibElemInst instance = new LibElemInst();
instance.AnchorLocation = t.Location;
instance.InstanceName = GetNextInstanceName();
instance.LibraryElementName = other.Name;
instance.SliceNumber = SliceNumber;
instance.SliceName = t.Slices[(int)SliceNumber].SliceName;
LibraryElementInstanceManager.Instance.Add(instance);
ExcludeInstantiationSourcesFromBlocking markSrc = new ExcludeInstantiationSourcesFromBlocking();
markSrc.AnchorLocation = t.Location;
markSrc.LibraryElementName = other.Name;
markSrc.CheckResources = checkResources;
// mark source as blocked, only check onces
checkResources = false;
CommandExecuter.Instance.Execute(markSrc);
SaveLibraryElementInstantiation saveCmd = new SaveLibraryElementInstantiation();
saveCmd.AddDesignConfig = false;
saveCmd.InsertPrefix = true;
saveCmd.InstanceName = instance.InstanceName;
saveCmd.NetlistContainerName = NetlistContainerName;
CommandExecuter.Instance.Execute(saveCmd);
}
}
else
{
// for normal moduleas use ISE code
AddISEInstantiation(t);
}
}
protected override void DoCommandAction()
{
PortMapping = Regex.Replace(PortMapping, "\\\"", "");
InstantiationFilter = Regex.Replace(InstantiationFilter, "\\\"", "");
Queue <LibElemInst> instantiations = new Queue <LibElemInst>();
Dictionary <string, bool> libraryElementNames = new Dictionary <string, bool>();
foreach (LibElemInst inst in LibraryElementInstanceManager.Instance.GetAllInstantiations())
{
// collect all macro names
if (!libraryElementNames.ContainsKey(inst.LibraryElementName))
{
libraryElementNames.Add(inst.LibraryElementName, false);
}
// filter
if (Regex.IsMatch(inst.InstanceName, InstantiationFilter))
{
instantiations.Enqueue(inst);
}
}
Dictionary <string, string> portMapping = PortMappingHandler.GetPortMapping(PortMapping);
Dictionary <string, int> indeces = new Dictionary <string, int>();
foreach (string key in portMapping.Keys)
{
indeces.Add(key, 0);
}
StringBuilder instanceCode = new StringBuilder();
SortedDictionary <string, int> signalWidths = new SortedDictionary <string, int>();
Dictionary <string, string> directions = new Dictionary <string, string>();
while (instantiations.Count > 0)
{
LibElemInst inst = instantiations.Dequeue();
LibraryElement libElement = Objects.Library.Instance.GetElement(inst.LibraryElementName);
instanceCode.AppendLine("-- instantiation of " + inst.InstanceName);
instanceCode.AppendLine(inst.InstanceName + " : " + libElement.PrimitiveName);
instanceCode.AppendLine("Port Map (");
List <string> mappings = new List <string>();
foreach (XDLPort port in ((XDLContainer)libElement.Containter).Ports)
{
string key;
if (PortMappingHandler.HasMapping(port, portMapping, out key))
{
string rightHandSide = portMapping[key];
// do not vectorize allready indeced ports
bool vector = Regex.IsMatch(port.ExternalName, @"\d+$") && !Regex.IsMatch(rightHandSide, @"\(\d+\)$");
bool constantAssigned = false;
if (rightHandSide.Equals("0"))
{
rightHandSide = "'" + rightHandSide + "'";
vector = false;
constantAssigned = true;
}
if (rightHandSide.Equals("1"))
{
rightHandSide = "'" + rightHandSide + "'";
vector = false;
constantAssigned = true;
}
if (vector && !rightHandSide.Equals("open"))
{
int index = indeces[key]++;
mappings.Add("\t" + port.ExternalName + " => " + rightHandSide + "(" + index + "),");
// store right hand sides for signal declarations
if (!signalWidths.ContainsKey(rightHandSide))
{
signalWidths.Add(rightHandSide, 0);
directions.Add(rightHandSide, port.Direction.ToString().ToLower());
}
else
{
signalWidths[rightHandSide]++;
}
}
else
{
mappings.Add("\t" + port.ExternalName + " => " + rightHandSide + ",");
if (!constantAssigned && !rightHandSide.Equals("open"))
{
if (!signalWidths.ContainsKey(rightHandSide))
{
signalWidths.Add(rightHandSide, 0);
}
if (!directions.ContainsKey(rightHandSide))
{
directions.Add(rightHandSide, port.Direction.ToString().ToLower());
}
else
{
if (!directions[rightHandSide].Equals(port.Direction.ToString().ToLower()))
{
throw new ArgumentException("Port direction changed for port " + port.ExternalName);
}
}
}
}
}
else
{
// no mapping, issue warning
OutputManager.WriteOutput("Warning: Could not find a right hand side for port " + port.ExternalName + ". Misspelled mapping? Note that the mapping is case sensistive.");
//mappings.Add("\t" + port.ExternalName + " => ,");
}
}
mappings[mappings.Count - 1] = Regex.Replace(mappings[mappings.Count - 1], ",$", "");
// update tool info
Tile t = FPGA.FPGA.Instance.GetTile(inst.AnchorLocation);
Blackboard.Instance.ClearToolTipInfo(t);
foreach (string str in mappings)
{
instanceCode.AppendLine(str);
// update tool info
if (!str.EndsWith(" => ,"))
{
string toolTip = str;
toolTip = Regex.Replace(toolTip, @"^\s+", "");
toolTip = Regex.Replace(toolTip, ",", "");
toolTip += Environment.NewLine;
Blackboard.Instance.AddToolTipInfo(t, toolTip);
}
}
instanceCode.AppendLine(");");
}
if (EmbedInstantionInEntity)
{
OutputManager.WriteVHDLOutput("library IEEE;");
OutputManager.WriteVHDLOutput("use IEEE.STD_LOGIC_1164.ALL;");
OutputManager.WriteVHDLOutput("");
OutputManager.WriteVHDLOutput("entity " + EntityName + " is port (");
// we need signalWidths as a list ...
List <KeyValuePair <string, int> > interfaceSignals = new List <KeyValuePair <string, int> >();
foreach (KeyValuePair <string, int> tupel in signalWidths)
{
interfaceSignals.Add(tupel);
}
for (int i = 0; i < interfaceSignals.Count; i++)
{
string signalName = interfaceSignals[i].Key;
string line = signalName + " : " + directions[signalName] + " std_logic_vector(" + interfaceSignals[i].Value + " downto 0)";
// ... to find the last index
if (i < interfaceSignals.Count - 1)
{
line += ";";
}
else
{
line += ");";
}
OutputManager.WriteVHDLOutput(line);
}
OutputManager.WriteVHDLOutput("end " + EntityName + ";");
OutputManager.WriteVHDLOutput("");
OutputManager.WriteVHDLOutput("architecture Behavioral of " + EntityName + " is");
OutputManager.WriteVHDLOutput("");
// use command
foreach (string libraryElementName in libraryElementNames.Keys)
{
PrintComponentDeclaration printWrapperCmd = new PrintComponentDeclaration();
printWrapperCmd.LibraryElement = libraryElementName;
printWrapperCmd.Do();
OutputManager.WriteVHDLOutput(printWrapperCmd.OutputManager.GetVHDLOuput());
}
OutputManager.WriteVHDLOutput("begin");
}
// print out signals declarations
if (PrintSignalDeclarations)
{
OutputManager.WriteVHDLOutput("--attribute s : string;");
foreach (KeyValuePair <string, int> tupel in signalWidths)
{
string decl = "signal " + tupel.Key + " : std_logic_vector(" + tupel.Value + " downto 0) := (others => '1');";
OutputManager.WriteVHDLOutput(decl);
}
foreach (KeyValuePair <string, int> tupel in signalWidths)
{
string attr = "attribute s of " + tupel.Key + " : signal is \"true\";";
OutputManager.WriteVHDLOutput(attr);
}
}
// print out instances
if (PrintInstantiations)
{
OutputManager.WriteVHDLOutput(instanceCode.ToString());
}
if (EmbedInstantionInEntity)
{
OutputManager.WriteVHDLOutput("end architecture Behavioral;");
}
}
