public void putBus_toUse(int pID, CacheAccessResult result, MESI_States pS, bool used = false)
{
if (this.waitingProcessors.Count == 0) //First entry into the queue else the bus would already be in use.
{
this.useCycles = 0;
this.inUse = true;
}
blockingInfo temp;
temp.processorId = pID;
temp.processorState = pS;
temp.result = result;
this.waitingProcessors.Enqueue(temp);
}
public void putBus_toUse(int pID, CacheAccessResult result, MESI_States pS, bool used = false)
{
if (this.waitingProcessors.Count == 0) //First entry into the queue else the bus would already be in use.
{
this.useCycles = 0;
this.inUse = true;
}
blockingInfo temp;
temp.processorId = pID;
temp.processorState = pS;
temp.result = result;
this.waitingProcessors.Enqueue(temp);
}
private void runOnTrace(int processorId, string line)
{
Label label;
CacheAccessResult result = CacheAccessResult.ReadHit; //This will change later. Simply assigned to avoid compilation error.
label = corresondingLabel(line[0]);
//Only need to simulate Data Cache
if (label != Label.Fetch)
{
//This means it is a memory access
processors[processorId].incrementMemoryAccess();
//Split the address to get the tag and slot
splitAddress(line.Substring(2));
if (existsInCache(processorId) == true) // Cache Hit
{
processors[processorId].incrementCacheHit();
if (label == Label.Read)
{
result = CacheAccessResult.ReadHit;
}
if (label == Label.Write)
{
result = CacheAccessResult.WriteHit;
}
}
else //Cache Miss
{
if (label == Label.Read)
{
result = CacheAccessResult.ReadMiss;
}
if (label == Label.Write)
{
result = CacheAccessResult.WriteMiss;
}
}
runCacheProtocol(result, processorId);
}
}
private void runCacheProtocol(CacheAccessResult currentResult, int processorId)
{
int slot = convertBinarytoDecimal(slotAddress);
switch (currentResult)
{
case CacheAccessResult.ReadHit: //No blocking. do nothing. There will be no state change and no bus use.
bus.pendingSignal.Enqueue(BusSignals.NoSignal);
break;
case CacheAccessResult.ReadMiss:
bus.pendingSignal.Enqueue(BusSignals.BusRd);
//block the processor
bus.putBus_toUse(processorId, currentResult, processors[processorId].L1.blocks[slot].currentState);
//currentProcessor will block
processors[processorId].isBlocked = true;
break;
case CacheAccessResult.WriteHit: //No blocking. //Can be because of being in MES state.
bus.pendingSignal.Enqueue(BusSignals.BusInvalidate);
break;
case CacheAccessResult.WriteMiss:
bus.pendingSignal.Enqueue(BusSignals.BusRdX);
//block the processor
bus.putBus_toUse(processorId, currentResult, processors[processorId].L1.blocks[slot].currentState);
//currentProcessor will block
processors[processorId].isBlocked = true;
break;
default:
break;
}
snoopBus(processorId);
}
private void runCacheProtocol(CacheAccessResult currentResult, int processorId)
{
int slot = convertBinarytoDecimal(slotAddress);
switch (currentResult)
{
case CacheAccessResult.ReadHit: //No blocking. do nothing. There will be no state change and no bus use.
bus.pendingSignal.Enqueue(BusSignals.NoSignal);
break;
case CacheAccessResult.ReadMiss:
bus.pendingSignal.Enqueue(BusSignals.BusRd);
//block the processor
bus.putBus_toUse(processorId, currentResult, processors[processorId].L1.blocks[slot].currentState);
//currentProcessor will block
processors[processorId].isBlocked = true;
break;
case CacheAccessResult.WriteHit: //No blocking. //Can be because of being in MES state.
bus.pendingSignal.Enqueue(BusSignals.BusInvalidate);
break;
case CacheAccessResult.WriteMiss:
bus.pendingSignal.Enqueue(BusSignals.BusRdX);
//block the processor
bus.putBus_toUse(processorId, currentResult, processors[processorId].L1.blocks[slot].currentState);
//currentProcessor will block
processors[processorId].isBlocked = true;
break;
default:
break;
}
snoopBus(processorId);
}
