/// <summary>
/// Constructs a new instance.
/// </summary>
/// <param name="project">ISE project</param>
public ToolFlow(XilinxProject project)
{
Project = project;
XST = new XSTFlow();
NGDBuild = new NGDBuildFlow();
Map = new MAPFlow();
PAR = new PARFlow();
TRCE = new TRCEFlow();
}
private void CreateUCF(XilinxProject proj)
{
string path = proj.AddFile(proj.ProjectName + ".ucf");
var sw = new StreamWriter(path);
foreach (var pin in PinList)
{
if (pin.AssociatedSignal == null)
{
continue;
}
string indexExpr = "";
if (pin.AssociatedIndex.Length > 0)
{
indexExpr = pin
.AssociatedIndex
.Select(i => "[" + i + "]")
.Aggregate((x, y) => x + y);
}
var sd = (ISignalOrPortDescriptor)((IDescriptive)pin.AssociatedSignal).Descriptor;
var pd = sd.AsSignalRef(SignalRef.EReferencedProperty.Instance)
.RelateToComponent(TopLevelComponent.Descriptor)
.Desc;
sw.WriteLine("NET \"{0}{1}\" LOC = {2};",
pd.Name, indexExpr, pin.Name);
}
foreach (IPortDescriptor pd in TopLevelComponent.Descriptor.GetPorts())
{
var sd = pd.BoundSignal;
if (sd == null)
{
continue;
}
var csa = sd.QueryAttribute <ClockSpecAttribute>();
if (csa == null)
{
continue;
}
sw.WriteLine("TIMESPEC TS_{0} = PERIOD \"{1}\" {2} {3};",
pd.Name, pd.Name, csa.Period.Value, csa.Period.Unit);
sw.WriteLine("NET \"{0}\" TNM_NET = \"{1}\";",
pd.Name, pd.Name);
}
sw.Close();
}
/// <summary>
/// Synthesizes the design.
/// </summary>
/// <param name="destPath">target path which will contain the generated files</param>
/// <param name="designName">name of the design</param>
/// <param name="info">ISE information</param>
/// <param name="twinProject">optional twin project</param>
/// <param name="step">what stages of the overall flow to execute</param>
/// <returns>the generated ISE project</returns>
public XilinxProject Synthesize(string destPath, string designName, ISEInfo info,
IProject twinProject = null, EFlowStep step = EFlowStep.HDLGenAndIPCores)
{
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(destPath, designName)
{
TwinProject = twinProject
};
project.ISEVersion = info.VersionTag;
if (info.Path == null)
{
project.SkipIPCoreSynthesis = true;
}
else
{
project.ISEBinPath = info.Path;
}
project.PutProperty(EXilinxProjectProperties.DeviceFamily, Device.GetFamily());
project.PutProperty(EXilinxProjectProperties.Device, Device);
project.PutProperty(EXilinxProjectProperties.Package, Package);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, SpeedGrade);
project.SetVHDLProfile();
if (!step.HasFlag(EFlowStep.IPCores))
{
project.SkipIPCoreSynthesis = true;
}
project.TopLevelComponent = TopLevelComponent.Descriptor;
CreateUCF(project);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(GetComponentSet(), codeGen);
project.Save();
if (step.HasFlag(EFlowStep.XST) ||
step.HasFlag(EFlowStep.NGDBuild) ||
step.HasFlag(EFlowStep.Map) ||
step.HasFlag(EFlowStep.PAR) ||
step.HasFlag(EFlowStep.TRCE))
{
var flow = project.ConfigureFlow(TopLevelComponent);
flow.Start(step);
}
return(project);
}
