private static bool Pre1w(uint uInstr, SuperHDisassembler dasm)
{
var reg = Registers.gpregs[(uInstr >> 8) & 0x0F];
dasm.state.ops.Add(MemoryOperand.IndirectPreDecr(PrimitiveType.Word16, reg));
return(true);
}
private static bool Pre15l(uint uInstr, SuperHDisassembler dasm)
{
var reg = Registers.r15;
dasm.state.ops.Add(MemoryOperand.IndirectPreDecr(PrimitiveType.Word32, reg));
return(true);
}
private SuperHInstruction Decode(ushort uInstr, Opcode opcode, string format)
{
var ops = new MachineOperand[2];
int iop = 0;
RegisterStorage reg;
PrimitiveType width;
for (int i = 0; i < format.Length; ++i)
{
switch (format[i])
{
case ',':
continue;
case '-': // predecrement
reg = Register(format[++i], uInstr);
ops[iop] = MemoryOperand.IndirectPreDecr(GetWidth(format[++i]), reg);
break;
case '+': // postdecrement
reg = Register(format[++i], uInstr);
ops[iop] = MemoryOperand.IndirectPostIncr(GetWidth(format[++i]), reg);
break;
case 'd':
ops[iop] = DfpRegister(format[++i], uInstr);
break;
case 'f':
ops[iop] = FpRegister(format[++i], uInstr);
break;
case 'r':
ops[iop] = new RegisterOperand(Register(format[++i], uInstr));
break;
case 'v':
ops[iop] = VfpRegister(format[++i], uInstr);
break;
case 'I':
ops[iop] = ImmediateOperand.Byte((byte)uInstr);
break;
case 'F':
if (format[++i] == 'U')
{
ops[iop] = new RegisterOperand(Registers.fpul);
break;
}
goto default;
case 'G':
ops[iop] = MemoryOperand.GbrIndexedIndirect(GetWidth(format[++i]));
break;
case '@':
reg = Register(format[++i], uInstr);
ops[iop] = MemoryOperand.Indirect(GetWidth(format[++i]), reg);
break;
case 'D': // indirect with displacement
reg = Register(format[++i], uInstr);
width = GetWidth(format[++i]);
ops[iop] = MemoryOperand.IndirectDisplacement(width, reg, (uInstr & 0xF) * width.Size);
break;
case 'X': // indirect indexed
reg = Register(format[++i], uInstr);
ops[iop] = MemoryOperand.IndexedIndirect(GetWidth(format[++i]), reg);
break;
case 'P': // PC-relative with displacement
width = GetWidth(format[++i]);
ops[iop] = MemoryOperand.PcRelativeDisplacement(width, width.Size * (byte)uInstr);
break;
case 'R':
++i;
if (format[i] == 'P')
ops[iop] = new RegisterOperand(Registers.pr);
else
ops[iop] = new RegisterOperand(Registers.gpregs[HexDigit(format[i]).Value]);
break;
case 'j':
ops[iop] = AddressOperand.Create(rdr.Address + (2 + 2 * (sbyte)uInstr));
break;
case 'J':
int offset = ((int)uInstr << 20) >> 19;
ops[iop] = AddressOperand.Create(rdr.Address + (2 + offset));
break;
case 'm': // Macl.
if (i < format.Length-1)
{
++i;
if (format[i] == 'l')
{
ops[iop] = new RegisterOperand(Registers.macl);
}
else if (format[i] == 'h')
{
ops[iop] = new RegisterOperand(Registers.mach);
}
else
{
throw new NotImplementedException(string.Format("m{0}", format[i]));
}
}
else
{
throw new NotImplementedException(string.Format("m{0}", format[i]));
}
break;
default: throw new NotImplementedException(string.Format("SuperHDisassembler.Decode({0})", format[i]));
}
++iop;
}
return new SuperHInstruction
{
Opcode = opcode,
op1 = ops[0],
op2 = ops[1],
};
}