private ConditionCode CcFromOperand(ConditionOperand ccOp)
{
switch (ccOp.condition & 3)
{
case 0: return ConditionCode.LT;
case 1: return ConditionCode.GT;
case 2: return ConditionCode.EQ;
case 3: return ConditionCode.OV;
default: throw new NotImplementedException();
}
}
private ConditionCode CcFromOperand(ConditionOperand ccOp)
{
switch (ccOp.condition & 3)
{
case 0: return(ConditionCode.LT);
case 1: return(ConditionCode.GT);
case 2: return(ConditionCode.EQ);
case 3: return(ConditionCode.OV);
default: throw new NotImplementedException();
}
}
public override PowerPcInstruction Decode(PowerPcDisassembler dasm, uint wInstr)
{
uint link = (wInstr & 1);
var uOffset = wInstr & 0x0000FFFC;
if ((uOffset & 0x8000) != 0)
{
uOffset |= 0xFFFF0000;
}
var grfBi = (wInstr >> 16) & 0x1F;
var grfBo = (wInstr >> 21) & 0x1F;
var crf = grfBi >> 2;
Opcode opcode;
InstrClass iclass = link == 1 ? InstrClass.Transfer | InstrClass.Call : InstrClass.Transfer;
MachineOperand op1;
MachineOperand op2;
var baseAddr = (wInstr & 2) != 0 ? Address.Create(dasm.defaultWordWidth, 0) : dasm.rdr.Address - 4;
var dst = new AddressOperand(baseAddr + uOffset);
switch (grfBo)
{
case 0:
case 1:
// Decrement ctr, branch if ctr != 0 and condition is false
opcode = opcBdnzf[link];
iclass |= InstrClass.Conditional;
op1 = new ConditionOperand(grfBi);
op2 = dst;
break;
case 2:
case 3:
// Decrement ctr, branch if ctr == 0 and condition is false
opcode = opcBdzf[link];
iclass |= InstrClass.Conditional;
op1 = new ConditionOperand(grfBi);
op2 = dst;
break;
case 4:
case 5:
case 6:
case 7:
// Branch if condition is false
opcode = opcBNcc[grfBi & 0b11, link];
private RegisterStorage CrFromOperand(ConditionOperand ccOp)
{
return(arch.CrRegisters[(int)ccOp.condition >> 2]);
}
private RegisterStorage CrFromOperand(ConditionOperand ccOp)
{
return arch.CrRegisters[(int)ccOp.condition >> 2];
}