public void Initialize()
{
cpu.EnableUncoreCounters();
for (uint cboIdx = 0; cboIdx < cpu.CboCount; cboIdx++)
{
// 0x34 = L3 lookups, 0xFF = all lookups
Ring0.WriteMsr(MSR_UNC_CBO_PERFEVTSEL0_base + MSR_UNC_CBO_increment * cboIdx,
GetUncorePerfEvtSelRegisterValue(0x34, 0xFF, false, false, true, false, 0));
// 0x34 = L3 lookups, high 4 bits = cacheable read | cacheable write | external snoop | irq/ipq
// low 4 bits = M | ES | I, so select I to count misses
Ring0.WriteMsr(MSR_UNC_CBO_PERFEVTSEL1_base + MSR_UNC_CBO_increment * cboIdx,
GetUncorePerfEvtSelRegisterValue(0x34, 0xF8, false, false, true, false, 0));
}
}
public void Initialize()
{
ThreadAffinity.Set(0x1);
cpu.EnableUncoreCounters();
for (uint cboIdx = 0; cboIdx < cpu.CboCount; cboIdx++)
{
// 0x22 = Snoop response, 0xFF = all responses
Ring0.WriteMsr(MSR_UNC_CBO_PERFEVTSEL0_base + MSR_UNC_CBO_increment * cboIdx,
GetUncorePerfEvtSelRegisterValue(0x22, 0xFF, false, false, true, false, 0));
// 0x22 = Snoop response, umask 0x4 = non-modified line hit, umask 0x8 = modified line hit
// high 3 bits of umask = filter. 0x20 = external snoop, 0x40 = core memory request, 0x80 = L3 eviction
Ring0.WriteMsr(MSR_UNC_CBO_PERFEVTSEL1_base + MSR_UNC_CBO_increment * cboIdx,
GetUncorePerfEvtSelRegisterValue(0x22, 0x4 | 0x8 | 0x20 | 0x40 | 0x80, false, false, true, false, 0));
}
}