/// <summary> /// Emits the specified platform instruction. /// </summary> /// <param name="node">The node.</param> /// <param name="emitter">The emitter.</param> /// <exception cref="System.NotSupportedException"></exception> protected override void Emit(InstructionNode node, MachineCodeEmitter emitter) { OpCode opcode; switch (node.ConditionCode) { case ConditionCode.Equal: opcode = E; break; case ConditionCode.LessThan: opcode = LT; break; case ConditionCode.LessOrEqual: opcode = LE; break; case ConditionCode.GreaterOrEqual: opcode = GE; break; case ConditionCode.GreaterThan: opcode = GT; break; case ConditionCode.NotEqual: opcode = NE; break; case ConditionCode.UnsignedGreaterOrEqual: opcode = UGE; break; case ConditionCode.UnsignedGreaterThan: opcode = UGT; break; case ConditionCode.UnsignedLessOrEqual: opcode = ULE; break; case ConditionCode.UnsignedLessThan: opcode = ULT; break; case ConditionCode.Parity: opcode = P; break; case ConditionCode.NoParity: opcode = NP; break; case ConditionCode.NoCarry: opcode = NC; break; case ConditionCode.Carry: opcode = C; break; case ConditionCode.Zero: opcode = Z; break; case ConditionCode.NotZero: opcode = NZ; break; default: throw new NotSupportedException(); } emitter.Emit(opcode, node.Result, null); }
/// <summary> /// Emits the specified platform instruction. /// </summary> /// <param name="node">The node.</param> /// <param name="emitter">The emitter.</param> /// <exception cref="System.InvalidOperationException">@unable to emit opcode for segment register</exception> protected override void Emit(InstructionNode node, MachineCodeEmitter emitter) { if (node.Operand1.IsConstant) { if (node.Operand1.IsByte) emitter.Emit(CONST8, node.Operand1); else if (node.Operand1.IsShort || node.Operand1.IsChar) emitter.Emit(CONST16, node.Operand1); else if (node.Operand1.IsInt) emitter.Emit(CONST32, node.Operand1); return; } if (node.Operand1.IsCPURegister) { if (node.Operand1.Register is SegmentRegister) switch ((node.Operand1.Register as SegmentRegister).Segment) { case SegmentRegister.SegmentType.CS: emitter.Emit(PUSH_CS); return; case SegmentRegister.SegmentType.SS: emitter.Emit(PUSH_SS); return; case SegmentRegister.SegmentType.DS: emitter.Emit(PUSH_DS); return; case SegmentRegister.SegmentType.ES: emitter.Emit(PUSH_ES); return; case SegmentRegister.SegmentType.FS: emitter.Emit(PUSH_FS); return; case SegmentRegister.SegmentType.GS: emitter.Emit(PUSH_GS); return; default: throw new InvalidOperationException(@"unable to emit opcode for segment register"); } } emitter.Emit(PUSH, node.Operand1); }
private static void MovImmediateToFixedMemory(InstructionNode node, MachineCodeEmitter emitter) { Debug.Assert(node.Operand1.IsConstant); Debug.Assert(node.Operand2.IsConstantZero); Debug.Assert(node.Operand3.IsConstant); Debug.Assert(node.ResultCount == 0); var linkreference = node.Operand3.IsLabel || node.Operand3.IsField || node.Operand3.IsSymbol; // immediate to memory 1100 011w: mod 000 r/m : immediate data var opcode = new OpcodeEncoder() .AppendConditionalPrefix(0x66, node.Size == InstructionSize.Size16) // 8:prefix: 16bit .AppendNibble(Bits.b1100) // 4:opcode .Append3Bits(Bits.b011) // 3:opcode .AppendWidthBit(node.Size != InstructionSize.Size8) // 1:width .AppendMod(Bits.b00) // 2:mod (000) .Append3Bits(Bits.b000) // 3:source (000) .AppendRM(node.Operand1) // 3:r/m (destination) .AppendConditionalDisplacement(node.Operand1, !linkreference) // 32:displacement value .AppendConditionalIntegerValue(0, linkreference) // 32:memory .AppendInteger(node.Operand3, node.Size); // 8/16/32:immediate if (linkreference) emitter.Emit(opcode, node.Operand1, (opcode.Size - (int)node.Size) / 8); else emitter.Emit(opcode); }
private static void MovsdRegToMemory(InstructionNode node, MachineCodeEmitter emitter) { Debug.Assert(node.Operand3.IsCPURegister); Debug.Assert(node.ResultCount == 0); Debug.Assert(!node.Operand3.IsConstant); // xmmreg1 to mem 1111 0010:0000 1111:0001 0001: mod xmmreg r/m var opcode = new OpcodeEncoder() .AppendNibble(Bits.b1111) // 4:opcode .AppendNibble(Bits.b0010) // 4:opcode .AppendNibble(Bits.b0000) // 4:opcode .AppendNibble(Bits.b1111) // 4:opcode .AppendNibble(Bits.b0001) // 4:opcode .AppendNibble(Bits.b0001) // 4:opcode // This opcode has a directionality bit, and it is set to 0 // This means we must swap around operand1 and operand3, and set offsetDestination to false .ModRegRMSIBDisplacement(false, node.Operand3, node.Operand1, node.Operand2) // Mod-Reg-RM-?SIB-?Displacement .AppendConditionalIntegerValue(node.Operand1.IsLinkerResolved, 0); // 32:memory if (node.Operand1.IsLinkerResolved) emitter.Emit(opcode, node.Operand1, (opcode.Size - 32) / 8); else emitter.Emit(opcode); }
/// <summary> /// Emits the constant operands. /// </summary> /// <param name="node">The node.</param> protected void EmitFloatingPointConstants(InstructionNode node) { for (int i = 0; i < node.OperandCount; i++) { var operand = node.GetOperand(i); if (operand == null || !operand.IsConstant || !operand.IsR) continue; if (operand.IsUnresolvedConstant) continue; var v1 = AllocateVirtualRegister(operand.Type); var symbol = (operand.IsR4) ? MethodCompiler.Linker.GetConstantSymbol(operand.ConstantSingleFloatingPoint) : MethodCompiler.Linker.GetConstantSymbol(operand.ConstantDoubleFloatingPoint); var s1 = Operand.CreateLabel(operand.Type, symbol.Name); var before = new Context(node).InsertBefore(); if (operand.IsR4) { before.SetInstruction(X86.MovssLoad, InstructionSize.Size32, v1, s1, ConstantZero); } else { before.SetInstruction(X86.MovsdLoad, InstructionSize.Size64, v1, s1, ConstantZero); } node.SetOperand(i, v1); } }
private static void MovImmediateToFixedMemory(InstructionNode node, MachineCodeEmitter emitter) { Debug.Assert(node.Operand1.IsConstant); Debug.Assert(node.Operand2.IsResolvedConstant); Debug.Assert(node.Operand3.IsConstant); // immediate to memory 1100 011w: mod 000 r/m : immediate data var opcode = new OpcodeEncoder() .AppendConditionalPrefix(node.Size == InstructionSize.Size16, 0x66) // 8:prefix: 16bit .AppendNibble(Bits.b1100) // 4:opcode .Append3Bits(Bits.b011) // 3:opcode .AppendWidthBit(node.Size != InstructionSize.Size8) // 1:width .AppendMod(Bits.b00) // 2:mod (00) .Append3Bits(Bits.b000) // 3:source (000) .AppendRM(node.Operand1) // 3:r/m (destination) .AppendConditionalDisplacement(!node.Operand1.IsLinkerResolved, node.Operand1) // 32:displacement value .AppendConditionalIntegerValue(node.Operand1.IsLinkerResolved, 0) // 32:memory .AppendInteger(node.Operand3, node.Size); // 8/16/32:immediate if (node.Operand1.IsLinkerResolved && !node.Operand3.IsLinkerResolved) emitter.Emit(opcode, node.Operand1, 2, node.Operand2.ConstantSignedInteger); else if (node.Operand1.IsLinkerResolved && node.Operand3.IsLinkerResolved) { // fixme: trouble! throw new NotImplementCompilerException("not here"); } else emitter.Emit(opcode); }
protected override void Emit(InstructionNode node, MachineCodeEmitter emitter) { Debug.Assert(node.Result.IsRegister); Debug.Assert(node.Operand1.IsRegister); Debug.Assert(node.Operand2.IsConstant); // reg from xmmreg, imm8 // 0110 0110:0000 1111:0011 1010: 0001 0110:11 xmmreg reg: imm8 var opcode = new OpcodeEncoder() .AppendNibble(Bits.b0110) // 4:opcode .AppendNibble(Bits.b0110) // 4:opcode .AppendNibble(Bits.b0000) // 4:opcode .AppendNibble(Bits.b1111) // 4:opcode .AppendNibble(Bits.b0011) // 4:opcode .AppendNibble(Bits.b1010) // 4:opcode .AppendNibble(Bits.b0001) // 4:opcode .AppendNibble(Bits.b0110) // 4:opcode .Append2Bits(Bits.b11) // 2:opcode .AppendRM(node.Operand1) // 3:r/m (source) .AppendRegister(node.Result.Register) // 3:register (destination) .AppendByteValue((byte)node.Operand2.ConstantUnsignedInteger); // 8:memory emitter.Emit(opcode); }
/// <summary> /// Converts the given instruction from three address format to a two address format. /// </summary> /// <param name="node">The conversion context.</param> private void ThreeTwoAddressConversion(InstructionNode node) { var instruction = node.Instruction as X86Instruction; if (instruction == null) return; if (!instruction.ThreeTwoAddressConversion) return; if (!(node.OperandCount >= 1 && node.ResultCount >= 1 && node.Result != node.Operand1)) return; Operand result = node.Result; Operand operand1 = node.Operand1; node.Operand1 = result; var move = GetMove(result, operand1); var size = GetInstructionSize(result.Type); var newNode = new InstructionNode(move, result, operand1); newNode.Size = size; node.Previous.Insert(newNode); return; }
/// <summary> /// Emits the specified platform instruction. /// </summary> /// <param name="node">The node.</param> /// <param name="emitter">The emitter.</param> protected override void Emit(InstructionNode node, MachineCodeEmitter emitter) { Debug.Assert(node.Result == null); OpCode opCode = ComputeOpCode(null, node.Operand1, node.Operand2); emitter.Emit(opCode, node.Operand1, node.Operand2); }
/// <summary> /// Emits the specified platform instruction. /// </summary> /// <param name="node">The node.</param> /// <param name="emitter">The emitter.</param> /// <exception cref="System.NotSupportedException"></exception> protected override void Emit(InstructionNode node, MachineCodeEmitter emitter) { byte[] opcode = null; switch (node.ConditionCode) { case ConditionCode.Equal: opcode = JE; break; case ConditionCode.NotEqual: opcode = JNE; break; case ConditionCode.Zero: opcode = JZ; break; case ConditionCode.NotZero: opcode = JNZ; break; case ConditionCode.GreaterOrEqual: opcode = JGE; break; case ConditionCode.GreaterThan: opcode = JG; break; case ConditionCode.LessOrEqual: opcode = JLE; break; case ConditionCode.LessThan: opcode = JL; break; case ConditionCode.UnsignedGreaterOrEqual: opcode = JAE; break; case ConditionCode.UnsignedGreaterThan: opcode = JA; break; case ConditionCode.UnsignedLessOrEqual: opcode = JBE; break; case ConditionCode.UnsignedLessThan: opcode = JB; break; case ConditionCode.Signed: opcode = JS; break; case ConditionCode.NotSigned: opcode = JNS; break; case ConditionCode.Carry: opcode = JC; break; case ConditionCode.NoCarry: opcode = JNC; break; case ConditionCode.Overflow: opcode = JO; break; case ConditionCode.NoOverflow: opcode = JNO; break; case ConditionCode.Parity: opcode = JP; break; case ConditionCode.NoParity: opcode = JNP; break; default: throw new NotSupportedException(); } emitter.EmitRelativeBranch(opcode, node.BranchTargets[0].Label); }
/// <summary> /// Emits the specified platform instruction. /// </summary> /// <param name="node">The node.</param> /// <param name="emitter">The emitter.</param> /// <exception cref="System.NotSupportedException"></exception> protected override void Emit(InstructionNode node, MachineCodeEmitter emitter) { OpCode opcode = null; switch (node.ConditionCode) { case ConditionCode.Equal: opcode = CMOVO; break; case ConditionCode.NotEqual: opcode = CMOVNE; break; case ConditionCode.Zero: opcode = CMOVZ; break; case ConditionCode.NotZero: opcode = CMOVNZ; break; case ConditionCode.GreaterOrEqual: opcode = CMOVGE; break; case ConditionCode.GreaterThan: opcode = CMOVG; break; case ConditionCode.LessOrEqual: opcode = CMOVLE; break; case ConditionCode.LessThan: opcode = CMOVL; break; case ConditionCode.UnsignedGreaterOrEqual: opcode = CMOVNB; break; case ConditionCode.UnsignedGreaterThan: opcode = CMOVA; break; case ConditionCode.UnsignedLessOrEqual: opcode = CMOVBE; break; case ConditionCode.UnsignedLessThan: opcode = CMOVB; break; case ConditionCode.Signed: opcode = CMOVS; break; case ConditionCode.NotSigned: opcode = CMOVNS; break; case ConditionCode.Carry: opcode = CMOVC; break; case ConditionCode.NoCarry: opcode = CMOVNC; break; case ConditionCode.Overflow: opcode = CMOVO; break; case ConditionCode.NoOverflow: opcode = CMOVNO; break; case ConditionCode.Parity: opcode = CMOVP; break; case ConditionCode.NoParity: opcode = CMOVNP; break; default: throw new NotSupportedException(); } emitter.Emit(opcode, node.Result, node.Operand1); }
private static void CmpXchg(InstructionNode node, MachineCodeEmitter emitter) { Debug.Assert(node.Result.IsRegister); Debug.Assert(node.Operand1.IsRegister); Debug.Assert(node.Operand2.IsRegister); Debug.Assert(node.GetOperand(3).IsRegister); Debug.Assert(node.Result.Register == GeneralPurposeRegister.EAX); Debug.Assert(node.Operand1.Register == GeneralPurposeRegister.EAX); Debug.Assert(node.ResultCount == 1); var linkreference = node.Operand2.IsLabel || node.Operand2.IsField || node.Operand2.IsSymbol; // Compare EAX with r/m32. If equal, ZF is set and r32 is loaded into r/m32. // Else, clear ZF and load r/m32 into EAX. // memory, register 0000 1111 : 1011 000w : mod reg r/m var opcode = new OpcodeEncoder() .AppendConditionalPrefix(0x66, node.Size == InstructionSize.Size16) // 8:prefix: 16bit .AppendNibble(Bits.b0000) // 4:opcode .AppendNibble(Bits.b1111) // 4:opcode .AppendNibble(Bits.b1011) // 4:opcode .Append3Bits(Bits.b000) // 3:opcode .AppendWidthBit(node.Size != InstructionSize.Size8) // 1:width .ModRegRMSIBDisplacement(node.GetOperand(3), node.Operand2, node.Operand3) // Mod-Reg-RM-?SIB-?Displacement .AppendConditionalIntegerValue(0, linkreference); // 32:memory if (linkreference) emitter.Emit(opcode, node.Operand1, (opcode.Size - 32) / 8); else emitter.Emit(opcode); }
/// <summary> /// Emits the specified platform instruction. /// </summary> /// <param name="node">The node.</param> /// <param name="emitter">The emitter.</param> protected override void Emit(InstructionNode node, MachineCodeEmitter emitter) { if (node.Operand3.IsConstant) { emitter.Emit(C, node.Operand2, node.Result, node.Operand3); } else { emitter.Emit(RM, node.Operand2, node.Result); } }
/// <summary> /// Emits the specified platform instruction. /// </summary> /// <param name="node">The node.</param> /// <param name="emitter">The emitter.</param> protected override void Emit(InstructionNode node, MachineCodeEmitter emitter) { if (node.Operand1.IsConstant && node.Result.IsCPURegister) { MovFixedMemoryToReg(node, emitter); } else { MovMemoryToReg(node, emitter); } }
/// <summary> /// Emits the specified platform instruction. /// </summary> /// <param name="node">The context.</param> /// <param name="emitter">The emitter.</param> protected override void Emit(InstructionNode node, MachineCodeEmitter emitter) { var opCode = ComputeOpCode(node.Size, node.Operand1, node.Operand2); if (node.Operand1.IsConstant) { emitter.Emit(opCode, node.Operand1, null); } else { emitter.Emit(opCode, null, null); } }
/// <summary> /// Emits the specified platform instruction. /// </summary> /// <param name="node">The node.</param> /// <param name="emitter">The emitter.</param> protected override void Emit(InstructionNode node, MachineCodeEmitter emitter) { OpCode opCode = ComputeOpCode(node.Result, node.Operand1, null); if (node.Result.Register is ControlRegister) { emitter.Emit(opCode, node.Result, node.Operand1); } else { emitter.Emit(opCode, node.Operand1, node.Result); } }
/// <summary> /// Emits the data processing instruction. /// </summary> /// <param name="node">The node.</param> /// <param name="emitter">The emitter.</param> /// <param name="opcode">The opcode.</param> /// <exception cref="InvalidCompilerException"></exception> protected void EmitDataProcessingInstruction(InstructionNode node, MachineCodeEmitter emitter, byte opcode) { if (node.Operand2.IsCPURegister && node.Operand3.IsShift) { emitter.EmitInstructionWithRegister(node.ConditionCode, opcode, node.UpdateStatus, node.Operand1.Register.Index, node.Result.Register.Index, node.Operand3.ShiftType, node.Operand2.Register.Index); } else if (node.Operand2.IsConstant && node.Operand3.IsConstant) { emitter.EmitInstructionWithImmediate(node.ConditionCode, opcode, node.UpdateStatus, node.Operand1.Register.Index, node.Result.Register.Index, (int)node.Operand2.ConstantSignedLongInteger, (int)node.Operand3.ConstantSignedLongInteger); } else { throw new InvalidCompilerException(); } }
private void LoadFirstOperandIntoRegister(InstructionNode node) { // load into a register Operand operand = node.Operand1; Operand register = AllocateVirtualRegister(operand.Type); node.Operand1 = register; var move = GetMove(register, operand); var size = GetInstructionSize(operand.Type); var newNode = new InstructionNode(move, register, operand); newNode.Size = size; node.Previous.Insert(newNode); }
/// <summary> /// Emits the specified platform instruction. /// </summary> /// <param name="node">The node.</param> /// <param name="emitter">The emitter.</param> protected override void Emit(InstructionNode node, MachineCodeEmitter emitter) { if (node.Operand1.IsConstant && node.Operand3.IsConstant) { MovImmediateToFixedMemory(node, emitter); } else if (node.Operand3.IsConstant || node.Operand3.IsLabel || node.Operand3.IsField || node.Operand3.IsSymbol) { MovImmediateToMemory(node, emitter); } else { MovRegToMemory(node, emitter); } }
private static void LeaAddress(InstructionNode node, MachineCodeEmitter emitter) { Debug.Assert(node.Result.IsCPURegister); // LEA – Load Effective Address 1000 1101 : modA reg r/m var opcode = new OpcodeEncoder() .AppendConditionalPrefix(node.Size == InstructionSize.Size16, 0x66) // 8:prefix: 16bit .AppendNibble(Bits.b1000) // 4:opcode .AppendNibble(Bits.b1101) // 3:opcode .ModRegRMSIBDisplacement(false, node.Result, node.Operand1, node.Operand2) // Mod-Reg-RM-?SIB-?Displacement .AppendConditionalIntegerValue(node.Operand1.IsLinkerResolved, 0); // 32:memory if (node.Operand1.IsLinkerResolved) emitter.Emit(opcode, node.Operand1, (opcode.Size - 32) / 8); else emitter.Emit(opcode); }
protected override void EmitInstruction(InstructionNode node, BaseCodeEmitter codeEmitter) { long start = codeEmitter.CurrentPosition; base.EmitInstruction(node, codeEmitter); long end = codeEmitter.CurrentPosition; var instruction = simAdapter.Convert(node, MethodCompiler.Method, BasicBlocks, (byte)(end - start)); if (instruction != null) { simLinker.AddInstruction(symbol, start, instruction); } simLinker.AddSourceInformation(symbol, start, node.SlotNumber.ToString() + "\t0x" + node.SlotNumber.ToString("X") + "\t" + node.Block.ToString() + "\t" + symbol + "\t" + node.ToString()); }
/// <summary> /// Converts the given instruction from three address format to a two address format. /// </summary> /// <param name="node">The conversion context.</param> private void ThreeTwoAddressConversion(InstructionNode node) { var instruction = node.Instruction as X86Instruction; if (instruction == null) return; if (!instruction.ThreeTwoAddressConversion) return; if (!(node.OperandCount >= 1 && node.ResultCount >= 1 && node.Result != node.Operand1)) return; Operand result = node.Result; Operand operand1 = node.Operand1; int label = node.Label; node.Operand1 = result; X86Instruction move = null; InstructionSize size = InstructionSize.None; if (result.Type.IsR4) { move = X86.Movss; size = InstructionSize.Size32; } else if (result.Type.IsR8) { move = X86.Movsd; size = InstructionSize.Size64; } else { move = X86.Mov; size = InstructionSize.Size32; } var newNode = new InstructionNode(move, result, operand1); newNode.Size = size; newNode.Label = label; node.Previous.Insert(newNode); return; }
private static void MovsxRegToReg(InstructionNode node, MachineCodeEmitter emitter) { Debug.Assert(node.Result.IsRegister); Debug.Assert(node.Operand1.IsRegister); // register2 to register1 0000 1111 : 1011 111w : 11 reg1 reg2 var opcode = new OpcodeEncoder() .AppendNibble(Bits.b0000) // 4:opcode .AppendNibble(Bits.b1111) // 4:opcode .AppendNibble(Bits.b1011) // 4:opcode .Append3Bits(Bits.b111) // 4:opcode .AppendWidthBit(node.Size != InstructionSize.Size8) // 1:width .AppendMod(Bits.b11) // 2:mod .AppendRegister(node.Result) // 3:register (destination) .AppendRM(node.Operand1); // 3:r/m (source) emitter.Emit(opcode); }
internal BasicBlock(int sequence, int label) { NextBlocks = new List<BasicBlock>(2); PreviousBlocks = new List<BasicBlock>(1); Label = label; Sequence = sequence; First = new InstructionNode(IRInstruction.BlockStart); First.Label = label; First.Block = this; Last = new InstructionNode(IRInstruction.BlockEnd); Last.Label = label; Last.Block = this; First.Next = Last; Last.Previous = First; }
private static void MovMemoryToReg(InstructionNode node, MachineCodeEmitter emitter) { Debug.Assert(node.Result.IsCPURegister); // memory to reg 1000 101w: mod reg r/m var opcode = new OpcodeEncoder() .AppendConditionalPrefix(node.Size == InstructionSize.Size16, 0x66) // 8:prefix: 16bit .AppendNibble(Bits.b1000) // 4:opcode .Append3Bits(Bits.b101) // 3:opcode .AppendWidthBit(node.Size != InstructionSize.Size8) // 1:width .ModRegRMSIBDisplacement(false, node.Result, node.Operand1, node.Operand2) // Mod-Reg-RM-?SIB-?Displacement .AppendConditionalIntegerValue(node.Operand1.IsLinkerResolved, 0); // 32:memory if (node.Operand1.IsLinkerResolved) emitter.Emit(opcode, node.Operand1, (opcode.Size - 32) / 8); else emitter.Emit(opcode); }
/// <summary> /// Emits the specified platform instruction. /// </summary> /// <param name="node">The node.</param> /// <param name="emitter">The emitter.</param> protected override void Emit(InstructionNode node, MachineCodeEmitter emitter) { if (node.OperandCount == 0) { emitter.EmitRelativeBranch(CALL, node.BranchTargets[0].Label); return; } if (node.Operand1.IsSymbol) { emitter.WriteByte(0xE8); emitter.EmitCallSite(node.Operand1); } else { emitter.Emit(RegCall, node.Operand1); } }
/// <summary> /// Emits the specified platform instruction. /// </summary> /// <param name="node">The node.</param> /// <param name="emitter">The emitter.</param> protected override void Emit(InstructionNode node, MachineCodeEmitter emitter) { if (node.Operand1 == null) { emitter.EmitRelativeBranch(JMP, node.BranchTargets[0].Label); } else { if (node.Operand1.IsSymbol) { emitter.WriteByte(0xE9); emitter.EmitCallSite(node.Operand1); } else if (node.Operand1.IsRegister) { emitter.Emit(JMP_R, node.Operand1); } } }
/// <summary> /// Emits the specified platform instruction. /// </summary> /// <param name="node">The node.</param> /// <param name="emitter">The emitter.</param> /// <exception cref="System.InvalidOperationException">@unable to emit opcode for segment register</exception> protected override void Emit(InstructionNode node, MachineCodeEmitter emitter) { if (node.Result.IsCPURegister) { if (node.Result.Register is SegmentRegister) switch ((node.Result.Register as SegmentRegister).Segment) { case SegmentRegister.SegmentType.DS: emitter.Emit(POP_DS); return; case SegmentRegister.SegmentType.ES: emitter.Emit(POP_ES); return; case SegmentRegister.SegmentType.FS: emitter.Emit(POP_FS); return; case SegmentRegister.SegmentType.GS: emitter.Emit(POP_GS); return; case SegmentRegister.SegmentType.SS: emitter.Emit(POP_SS); return; default: throw new InvalidOperationException(@"unable to emit opcode for segment register"); } else emitter.WriteByte((byte)(0x58 + node.Result.Register.RegisterCode)); } else emitter.Emit(POP, node.Result); }
private static void MovapsMemoryToReg(InstructionNode node, MachineCodeEmitter emitter) { Debug.Assert(node.Result.IsCPURegister); // mem to xmmreg 1111 0011:0000 1111:0101 1101: mod xmmreg r/m var opcode = new OpcodeEncoder() .AppendNibble(Bits.b1111) // 4:opcode .AppendNibble(Bits.b0011) // 4:opcode .AppendNibble(Bits.b0000) // 4:opcode .AppendNibble(Bits.b1111) // 4:opcode .AppendNibble(Bits.b0101) // 4:opcode .AppendNibble(Bits.b1101) // 4:opcode .ModRegRMSIBDisplacement(false, node.Result, node.Operand1, node.Operand2) // Mod-Reg-RM-?SIB-?Displacement .AppendConditionalIntegerValue(node.Operand1.IsLinkerResolved, 0); // 32:memory if (node.Operand1.IsLinkerResolved) emitter.Emit(opcode, node.Operand1, (opcode.Size - 32) / 8); else emitter.Emit(opcode); }
private static void LgdtMemoryConstant(InstructionNode node, MachineCodeEmitter emitter) { Debug.Assert(node.Operand1.IsConstant); // LGDT – Load Global Descriptor Table Register 0000 1111 : 0000 0001 : modA 010 r / m var opcode = new OpcodeEncoder() .AppendNibble(Bits.b0000) // 4:opcode .AppendNibble(Bits.b1111) // 4:opcode .AppendNibble(Bits.b0000) // 4:opcode .AppendNibble(Bits.b0001) // 4:opcode .Append2Bits(Bits.b00) // 2:mod (must not be b11) .Append3Bits(Bits.b010) // 3:reg .AppendRM(node.Operand1) // 3:r/m (source, always b101) .AppendConditionalDisplacement(!node.Operand1.IsConstantZero, node.Operand1) // 32:displacement value .AppendConditionalIntegerValue(node.Operand1.IsLinkerResolved, 0); // 32:memory if (node.Operand1.IsLinkerResolved) emitter.Emit(opcode, node.Operand1, (opcode.Size - 32) / 8); else emitter.Emit(opcode); }
public OperandVisitor(InstructionNode node) { this.node = node; }
/// <summary> /// Initializes a new instance of the <see cref="Context" /> class. /// </summary> /// <param name="instructionNode">The instruction node.</param> public Context(InstructionNode instructionNode) { Node = instructionNode; }