public virtual void count_queueing(Cmd cmd)
{
if (cmd == null)
{
return;
}
Req req = cmd.req;
MemCtrl mctrl = meta_mctrl.get_mctrl(req);
ulong shadow_rowid = mctrl.shadow_rowid_per_procrankbank[req.pid, req.addr.rid, req.addr.bid];
ulong rowid = mctrl.rowid_per_procrankbank[req.addr.rid, req.addr.bid];
if (Config.stride_prefetcher_on)
{
if (!req.is_prefetch && shadow_rowid == req.addr.rowid && rowid != req.addr.rowid)
{
meta_mctrl.rbhit_interference_addr[req.pid] = req.addr.rowid;
meta_mctrl.interference_bit_rowbuffer[req.pid] = true;
}
}
else
{
if (shadow_rowid == req.addr.rowid && rowid != req.addr.rowid)
{
meta_mctrl.rbhit_interference_addr[req.pid] = req.addr.rowid;
meta_mctrl.interference_bit_rowbuffer[req.pid] = true;
}
}
return;
}
private bool is_idle(uint cid)
{
if (!rmpkis_valid)
{
return(false);
}
if (low_rmpki_cnt == 0)
{
return(false);
}
MemCtrl mctrl = mctrls[cid];
if (mctrl.wload < 0.25 * mctrl.mctrl_writeq.Capacity)
{
return(false);
}
for (int pid = 0; pid < Config.N; pid++)
{
if (!is_low_rmpki[pid])
{
continue;
}
if (mctrl.rload_per_proc[pid] > 0)
{
return(false);
}
}
return(true);
}
private bool is_readq_idle(uint cid)
{
if (!rmpkis_valid)
{
return(false);
}
if (low_rmpki_cnt == 0)
{
return(false);
}
MemCtrl mctrl = mctrls[cid];
for (int pid = 0; pid < Config.N; pid++)
{
if (!is_low_rmpki[pid])
{
continue;
}
if (mctrl.rload_per_proc[pid] > 0)
{
return(false);
}
}
return(true);
}
public bool is_row_hit(Req req)
{
MemCtrl mctrl = get_mctrl(req);
Bank bank = mctrl.chan.ranks[req.addr.rid].banks[req.addr.bid];
return(bank.curr_rowid == (long)req.addr.rowid);
}
//non-omniscient
public MetaMemCtrl(MemCtrl mctrl, MemSched sched, MemSched wbsched)
{
is_omniscient = false;
this.mctrl = mctrl;
this.mctrls = new MemCtrl[] { mctrl };
this.sched = sched;
this.wbsched = wbsched;
set_banks();
}
//non-omniscient
public MetaMemCtrl(MemCtrl mctrl, MemSched sched, MemSched wbsched)
{
is_omniscient = false;
this.mctrl = mctrl;
this.mctrls = new MemCtrl[] { mctrl };
this.sched = sched;
this.wbsched = wbsched;
set_banks();
}
//constructor
public Bank(MemCtrl mc, Rank rank, uint bid)
{
this.cid = mc.cid;
this.rid = rank.rid;
this.bid = bid;
this.mc = mc;
curr_rowid = -1; //closed-row
}
//constructor
public Bank(MemCtrl mc, Rank rank, uint bid) {
this.cid = mc.cid;
this.rid = rank.rid;
this.bid = bid;
this.mc = mc;
curr_rowid = -1; //closed-row
curr_proc = int.MaxValue;
}
//omniscient
public MetaMemCtrl(MemCtrl[] mctrls, MemSched sched, MemSched wbsched)
{
is_omniscient = true;
this.mctrl = null;
this.mctrls = mctrls;
this.sched = sched;
this.wbsched = wbsched;
set_banks();
}
//omniscient
public MetaMemCtrl(MemCtrl[] mctrls, MemSched sched, MemSched wbsched)
{
is_omniscient = true;
this.mctrl = null;
this.mctrls = mctrls;
this.sched = sched;
this.wbsched = wbsched;
set_banks();
}
//constructor
public Channel(MemCtrl mc, uint rmax, uint bmax)
{
this.cid = mc.cid;
this.mc = mc;
this.rmax = rmax;
ranks = new Rank[rmax];
for (uint i = 0; i < ranks.Length; i++) {
ranks[i] = new Rank(mc, this, i, bmax);
}
}
//constructor
public Channel(MemCtrl mc, uint rmax, uint bmax)
{
this.cid = mc.cid;
this.mc = mc;
this.rmax = rmax;
ranks = new Rank[rmax];
for (uint i = 0; i < ranks.Length; i++)
{
ranks[i] = new Rank(mc, this, i, bmax);
}
}
//constructor
public Rank(MemCtrl mc, Channel chan, uint rid, uint bmax)
{
this.cid = mc.cid;
this.rid = rid;
this.mc = mc;
this.bmax = bmax;
banks = new Bank[bmax];
for (uint i = 0; i < banks.Length; i++) {
banks[i] = new Bank(mc, this, i);
}
}
//constructor
public Rank(MemCtrl mc, Channel chan, uint rid, uint bmax)
{
this.cid = mc.cid;
this.rid = rid;
this.mc = mc;
this.bmax = bmax;
banks = new Bank[bmax];
for (uint i = 0; i < banks.Length; i++) {
banks[i] = new Bank(mc, this, i);
}
}
public Req get_curr_req(Bank bank)
{
MemCtrl mc = bank.mc;
List <Req> inflight_q = mc.inflightqs[bank.rid, bank.bid];
if (inflight_q.Count == 0)
{
return(null);
}
return(inflight_q[inflight_q.Count - 1]);
}
public Cmd get_curr_served_req(Bank bank)
{
MemCtrl mc = bank.mc;
List <Cmd> cmd_q = mc.cmdqs[bank.rid, bank.bid];
if (cmd_q.Count == 0)
{
return(null);
}
return(cmd_q[0]);
}
public override void issue_req(Req req)
{
if (req == null)
{
return;
}
MemCtrl mctrl = meta_mctrl.get_mctrl(req);
ulong shadow_rowid = mctrl.shadow_rowid_per_procrankbank[req.pid, req.addr.rid, req.addr.bid];
if (shadow_rowid == req.addr.rowid)
{
shadow_row_hits[req.pid]++;
}
}
public bool is_req_to_cur_proc(Req req)
{
MemCtrl mctrl = get_mctrl(req);
Bank bank = mctrl.chan.ranks[req.addr.rid].banks[req.addr.bid];
Req curr_req = get_curr_req(bank);
if (curr_req != null)
{
return(curr_req.pid == (long)req.pid);
}
else
{
return(false);
}
}
public override void count_queueing(Cmd cmd)
{
if (cmd == null)
{
return;
}
Req req = cmd.req;
MemCtrl mctrl = meta_mctrl.get_mctrl(req);
ulong shadow_rowid = mctrl.shadow_rowid_per_procrankbank[req.pid, req.addr.rid, req.addr.bid];
ulong rowid = mctrl.rowid_per_procrankbank[req.addr.rid, req.addr.bid];
if (shadow_rowid == req.addr.rowid && rowid != req.addr.rowid)
{
t_interference_rhit[req.pid] += 150;
}
}
//constructor
public BLPTracker(MemCtrl[] mctrls)
{
this.mctrls = mctrls;
//banks
banks = new List<Bank>();
foreach (MemCtrl mc in this.mctrls) {
Channel chan = mc.chan;
for (uint r = 0; r < chan.rmax; r++) {
Rank rank = chan.ranks[r];
for (uint b = 0; b < rank.bmax; b++) {
Bank bank = rank.banks[b];
banks.Add(bank);
}
}
}
//blp
blp_perproc = new int[Config.N];
}
public bool proc_req_in_queue(int cur_proc)
{
if (!is_omniscient)
{
foreach (Bank b in banks)
{
MemCtrl mc = b.mc;
List <Req> read_q = mc.readqs[b.rid, b.bid];
for (int i = 0; i < read_q.Count; i++)
{
if (!mctrl.mwbmode.is_wb_mode(b.cid) && read_q[i].pid == cur_proc)
{
return(true);
}
}
}
return(false);
}
else
{
for (uint r = 0; r < mctrls[0].chan.rmax; r++)
{
for (uint b = 0; b < mctrls[0].chan.ranks[r].bmax; b++)
{
List <Req> read_q = mctrls[0].chan.ranks[r].banks[b].mc.readqs[mctrls[0].chan.ranks[r].banks[b].rid, mctrls[0].chan.ranks[r].banks[b].bid];
for (int i = 0; i < read_q.Count; i++)
{
if (!mctrls[0].mwbmode.is_wb_mode(mctrls[0].chan.ranks[r].banks[b].cid) && read_q[i].pid == cur_proc)
{
return(true);
}
}
}
}
return(false);
}
}
public bool proc_req_in_queue(int cur_proc, Bank bank)
{
MemCtrl mc = bank.mc;
List <Req> read_q = mc.readqs[bank.rid, bank.bid];
for (int i = 0; i < read_q.Count; i++)
{
if (read_q[i].pid == cur_proc)
{
foreach (Req r in Sim.procs[read_q[i].pid].mshr)
{
if (r.block_addr == read_q[i].block_addr)
{
r.interference_cycles++;
}
}
}
}
for (int i = 0; i < read_q.Count; i++)
{
if (Config.stride_prefetcher_on)
{
if (!read_q[i].is_prefetch && read_q[i].pid == cur_proc)
{
return(true);
}
}
else
{
if (read_q[i].pid == cur_proc)
{
return(true);
}
}
}
return(false);
}
static void initialize()
{
//processors
//crossbar
xbar = new Xbar();
//ddr3
DDR3DRAM ddr3 = new DDR3DRAM(Config.mem.ddr3_type, Config.mem.clock_factor, Config.mem.tWR, Config.mem.tWTR);
uint cmax = (uint)Config.mem.channel_max;
uint rmax = (uint)Config.mem.rank_max;
//randomized page table
ulong page_size = 4 * 1024;
PageRandomizer prand = new PageRandomizer(page_size);
Req.prand = prand;
Console.Write("Initializing prand\n");
//sequential page table
PageSequencer pseq = new PageSequencer(page_size, cmax, rmax, ddr3.BANK_MAX);
Req.pseq = pseq;
if (Config.is_shared_cache)
{
Console.Write("Initializing shared cache\n");
shared_cache = new Cache();
}
else
{
Console.Write("Initializing private cache\n");
shared_cache = null;
}
procs = new Proc[Config.N];
for (int p = 0; p < Config.N; p++) {
if (shared_cache == null)
procs[p] = new Proc(new Cache(), new L1Cache(), Config.traceFileNames[p]);
else
{
Console.Write("Shared\n");
procs[p] = new Proc(shared_cache, new L1Cache(), Config.traceFileNames[p]);
}
}
Console.Write(" periodic dump " + Config.periodic_dump + "\n");
if (Config.periodic_dump)
{
rep_name_periodic_ipc = Config.periodic_name + "_ipc_periodic.txt";
Console.Write("Creating IPC periodic file\n");
periodic_writer_ipc = File.CreateText(rep_name_periodic_ipc);
}
//memory mapping
MemMap.init(Config.mem.map_type, Config.mem.channel_max, Config.mem.rank_max, Config.mem.col_per_subrow, ddr3);
//memory controllers
mctrls = new MemCtrl[cmax];
for (int i = 0; i < mctrls.Length; i++) {
mctrls[i] = new MemCtrl(rmax, ddr3);
}
//memory schedulers and metamemory controllers
if (!Config.sched.is_omniscient) {
MemSched[] scheds = new MemSched[cmax];
for (int i = 0; i < cmax; i++) {
scheds[i] = Activator.CreateInstance(Config.sched.typeof_sched_algo) as MemSched;
}
MemSched[] wbscheds = new MemSched[cmax];
if (!Config.sched.same_sched_algo) {
for (int i = 0; i < cmax; i++) {
wbscheds[i] = Activator.CreateInstance(Config.sched.typeof_wbsched_algo) as MemSched;
}
}
else {
for (int i = 0; i < cmax; i++) {
wbscheds[i] = scheds[i];
}
}
MetaMemCtrl[] meta_mctrls = new MetaMemCtrl[cmax];
for (int i = 0; i < cmax; i++) {
meta_mctrls[i] = new MetaMemCtrl(mctrls[i], scheds[i], wbscheds[i]);
mctrls[i].meta_mctrl = meta_mctrls[i];
scheds[i].meta_mctrl = meta_mctrls[i];
scheds[i].initialize();
wbscheds[i].meta_mctrl = meta_mctrls[i];
wbscheds[i].initialize();
}
}
else {
MemSched sched = Activator.CreateInstance(Config.sched.typeof_sched_algo) as MemSched;
MemSched wbsched;
if (!Config.sched.same_sched_algo) {
wbsched = Activator.CreateInstance(Config.sched.typeof_wbsched_algo) as MemSched;
}
else {
wbsched = sched;
}
MetaMemCtrl meta_mctrl = new MetaMemCtrl(mctrls, sched, wbsched);
for (int i = 0; i < cmax; i++) {
mctrls[i].meta_mctrl = meta_mctrl;
}
sched.meta_mctrl = meta_mctrl;
sched.initialize();
wbsched.meta_mctrl = meta_mctrl;
wbsched.initialize();
}
//wbmode
mwbmode = Activator.CreateInstance(Config.mctrl.typeof_wbmode_algo, new Object[] { mctrls }) as MemWBMode;
for (int i = 0; i < cmax; i++) {
mctrls[i].mwbmode = mwbmode;
}
//blp tracker
blptracker = new BLPTracker(mctrls);
}
public DecoupledWBFullDrain(MemCtrl[] mctrls)
: base(mctrls)
{
}
public RowHitFinder(MemCtrl mctrl)
{
this.mctrl = mctrl;
}
public MemWBMode(MemCtrl[] mctrls)
{
this.cmax = mctrls.Length;
this.mctrls = mctrls;
this.wb_mode = new bool[cmax];
}
public static void UpdateDict(Dictionary <ulong, AccessInfo> dict, Req req, MemCtrl mctrl)
{//Need to update NVM dictionary when a request comes out of L2
//Need to update both dictionary when a request
AccessInfo temp;
if (!dict.ContainsKey(KeyGen(req)))
{//If dictionary does not have this record
temp.ReadMiss = 0;
temp.WriteMiss = 0;
temp.ReadHit = 0;
temp.WriteHit = 0;
temp.Access = 1;
temp.ReadMLPnum = 1;
temp.WriteMLPnum = 1;
temp.ReadMLPAcc = 0;
temp.ReadMLPTimes = 0;
temp.WriteMLPAcc = 0;
temp.WriteMLPTimes = 0;
temp.pid = req.pid;
temp.addlist = false;
//not in the dictionary means a cold miss
if (req.type == ReqType.RD)
{
temp.ReadMiss++;
}
else
{
temp.WriteMiss++;
}
dict.Add(KeyGen(req), temp);
NVMLookUp.Add(KeyGen(req));
}
else
{//If dictionary has this record
temp = dict[KeyGen(req)];
temp.Access++;
RowHitFinder rhf = new RowHitFinder(mctrl);
if (rhf.is_row_hit(req)) // a hit
{
if (req.type == ReqType.RD)
{
temp.ReadHit++;
}
else
{
temp.WriteHit++;
}
}
else
{
if (req.type == ReqType.RD)
{
temp.ReadMiss++;
}
else
{
temp.WriteMiss++;
}
}
dict[KeyGen(req)] = temp;
}
RowCache.NVMCache.insert(KeyGen(req));
}
public DecoupledRDEmptyDrain(MemCtrl[] mctrls)
: base(mctrls)
{
}
public DecoupledWBFullServeN(MemCtrl[] mctrls)
: base(mctrls)
{
serve_max = Config.mctrl.serve_max;
serve_cnt = new uint[cmax];
}
protected bool is_writeq_full(uint cid)
{
MemCtrl mctrl = mctrls[cid];
return(mctrl.mctrl_writeq.Capacity == mctrl.wload);
}
protected bool is_readq_empty(uint cid)
{
MemCtrl mctrl = mctrls[cid];
return(mctrl.rload == 0);
}
static void initialize()
{
//processors
//crossbar
xbar = new Xbar();
//ddr3
DDR3DRAM ddr3 = new DDR3DRAM(Config.mem.ddr3_type, Config.mem.clock_factor, Config.mem.tWR, Config.mem.tWTR);
uint cmax = (uint)Config.mem.channel_max;
uint rmax = (uint)Config.mem.rank_max;
//randomized page table
ulong page_size = 4 * 1024;
PageRandomizer prand = new PageRandomizer(page_size);
Req.prand = prand;
Console.Write("Initializing prand\n");
//sequential page table
PageSequencer pseq = new PageSequencer(page_size, cmax, rmax, ddr3.BANK_MAX);
Req.pseq = pseq;
if (Config.is_shared_cache)
{
Console.Write("Initializing shared cache\n");
shared_cache = new Cache();
}
else
{
Console.Write("Initializing private cache\n");
shared_cache = null;
}
procs = new Proc[Config.N];
for (int p = 0; p < Config.N; p++)
{
if (shared_cache == null)
{
procs[p] = new Proc(new Cache(), new L1Cache(), Config.traceFileNames[p]);
}
else
{
Console.Write("Shared\n");
procs[p] = new Proc(shared_cache, new L1Cache(), Config.traceFileNames[p]);
}
}
Console.Write(" periodic dump " + Config.periodic_dump + "\n");
if (Config.periodic_dump)
{
rep_name_periodic_ipc = Config.periodic_name + "_ipc_periodic.txt";
Console.Write("Creating IPC periodic file\n");
periodic_writer_ipc = File.CreateText(rep_name_periodic_ipc);
}
//memory mapping
MemMap.init(Config.mem.map_type, Config.mem.channel_max, Config.mem.rank_max, Config.mem.col_per_subrow, ddr3);
//memory controllers
mctrls = new MemCtrl[cmax];
for (int i = 0; i < mctrls.Length; i++)
{
mctrls[i] = new MemCtrl(rmax, ddr3);
}
//memory schedulers and metamemory controllers
if (!Config.sched.is_omniscient)
{
MemSched[] scheds = new MemSched[cmax];
for (int i = 0; i < cmax; i++)
{
scheds[i] = Activator.CreateInstance(Config.sched.typeof_sched_algo) as MemSched;
}
MemSched[] wbscheds = new MemSched[cmax];
if (!Config.sched.same_sched_algo)
{
for (int i = 0; i < cmax; i++)
{
wbscheds[i] = Activator.CreateInstance(Config.sched.typeof_wbsched_algo) as MemSched;
}
}
else
{
for (int i = 0; i < cmax; i++)
{
wbscheds[i] = scheds[i];
}
}
MetaMemCtrl[] meta_mctrls = new MetaMemCtrl[cmax];
for (int i = 0; i < cmax; i++)
{
meta_mctrls[i] = new MetaMemCtrl(mctrls[i], scheds[i], wbscheds[i]);
mctrls[i].meta_mctrl = meta_mctrls[i];
scheds[i].meta_mctrl = meta_mctrls[i];
scheds[i].initialize();
wbscheds[i].meta_mctrl = meta_mctrls[i];
wbscheds[i].initialize();
}
}
else
{
MemSched sched = Activator.CreateInstance(Config.sched.typeof_sched_algo) as MemSched;
MemSched wbsched;
if (!Config.sched.same_sched_algo)
{
wbsched = Activator.CreateInstance(Config.sched.typeof_wbsched_algo) as MemSched;
}
else
{
wbsched = sched;
}
MetaMemCtrl meta_mctrl = new MetaMemCtrl(mctrls, sched, wbsched);
for (int i = 0; i < cmax; i++)
{
mctrls[i].meta_mctrl = meta_mctrl;
}
sched.meta_mctrl = meta_mctrl;
sched.initialize();
wbsched.meta_mctrl = meta_mctrl;
wbsched.initialize();
}
//wbmode
mwbmode = Activator.CreateInstance(Config.mctrl.typeof_wbmode_algo, new Object[] { mctrls }) as MemWBMode;
for (int i = 0; i < cmax; i++)
{
mctrls[i].mwbmode = mwbmode;
}
//blp tracker
blptracker = new BLPTracker(mctrls);
}
static void initialize()
{
if (Config.task_based == true)
{
string task_fname = Config.traceFileNames[0];
if (Config.sim_type == Config.SIM_TYPE.GROUPED)
{
task_fname = Config.traceFileNames[Config.group_boundary];
}
foreach (string dir in Config.TraceDirs.Split(',', ' '))
{
if (File.Exists(dir + "/" + task_fname))
{
task_fname = dir + "/" + task_fname;
}
}
Dbg.Assert(File.Exists(task_fname));
StreamReader tasks = new StreamReader(File.OpenRead(task_fname));
while (true)
{
string line = tasks.ReadLine();
if (line == null)
{
break;
}
task_queue.Enqueue(line);
}
tasks.Close();
}
Dram_Utilization_size = 0;
Dram_req_num = 0;
NVM_req_num = 0;
//randomized page table
ulong page_size = 4 * 1024;
PageRandomizer prand = new PageRandomizer(page_size);
Req.prand = prand;
//processors
procs = new Proc[Config.N];
for (int p = 0; p < Config.N; p++)
{
if ((Config.task_based == true && Config.sim_type != Config.SIM_TYPE.GROUPED) ||
(Config.task_based == true && Config.sim_type == Config.SIM_TYPE.GROUPED && p >= Config.group_boundary && p < Config.N))
{
procs[p] = new Proc(task_queue.Dequeue());
}
else
{
procs[p] = new Proc(Config.traceFileNames[p]);
}
}
//crossbar
xbar = new Xbar();
// warmup phase
proc_warmup = new bool[Config.N];
proc_warmup_cycles = new ulong[Config.N];
for (int p = 0; p < Config.N; p++)
{
proc_warmup[p] = false;
proc_warmup_cycles[p] = 0;
}
// Power Measurement:
processor_finished = new bool[Config.N];
DRAM_processor_read_hit = new ulong[Config.N];
DRAM_processor_read_miss = new ulong[Config.N];
DRAM_processor_write_hit = new ulong[Config.N];
DRAM_processor_write_miss = new ulong[Config.N];
DRAM_migration_read_hit = new ulong[Config.N];
DRAM_migration_read_miss = new ulong[Config.N];
DRAM_migration_write_hit = new ulong[Config.N];
DRAM_migration_write_miss = new ulong[Config.N];
NVM_processor_read_hit = new ulong[Config.N];
NVM_processor_read_miss = new ulong[Config.N];
NVM_processor_write_hit = new ulong[Config.N];
NVM_processor_write_miss = new ulong[Config.N];
NVM_migration_read_hit = new ulong[Config.N];
NVM_migration_read_miss = new ulong[Config.N];
NVM_migration_write_hit = new ulong[Config.N];
NVM_migration_write_miss = new ulong[Config.N];
processor_cycles = new ulong[Config.N];
for (int p = 0; p < Config.N; p++)
{
processor_finished[p] = false;
DRAM_processor_read_hit[p] = 0;
DRAM_processor_read_miss[p] = 0;
DRAM_processor_write_hit[p] = 0;
DRAM_processor_write_miss[p] = 0;
DRAM_migration_read_hit[p] = 0;
DRAM_migration_read_miss[p] = 0;
DRAM_migration_write_hit[p] = 0;
DRAM_migration_write_miss[p] = 0;
NVM_processor_read_hit[p] = 0;
NVM_processor_read_miss[p] = 0;
NVM_processor_write_hit[p] = 0;
NVM_processor_write_miss[p] = 0;
NVM_migration_read_hit[p] = 0;
NVM_migration_read_miss[p] = 0;
NVM_migration_write_hit[p] = 0;
NVM_migration_write_miss[p] = 0;
processor_cycles[p] = 0;
}
//
//Jin: Row Migration Policies
rmp = new Row_Migration_Policies();
mesur = new Measurement();
//ddr3
DDR3DRAM ddr3 = new DDR3DRAM(Config.mem.ddr3_type, Config.mem.clock_factor, Config.mem.tWR, Config.mem.tWTR);
uint cmax = (uint)Config.mem.channel_max;
uint rmax = (uint)Config.mem.rank_max;
//sequential page table
PageSequencer pseq = new PageSequencer(page_size, cmax, rmax, ddr3.BANK_MAX);
Req.pseq = pseq;
//memory mapping
MemMap.init(Config.mem.map_type, Config.mem.channel_max, Config.mem.rank_max, Config.mem.col_per_subrow, ddr3);
//memory controllers
mctrls = new MemCtrl[Config.mem.mctrl_num][];
for (int n = 0; n < Config.mem.mctrl_num; n++)
{
mctrls[n] = new MemCtrl[cmax];
for (int i = 0; i < mctrls[n].Length; i++)
{
mctrls[n][i] = new MemCtrl(rmax, ddr3);
}
}
//memory schedulers and metamemory controllers
if (!Config.sched.is_omniscient)
{
MemSched[][] scheds = new MemSched[Config.mem.mctrl_num][];
for (int n = 0; n < Config.mem.mctrl_num; n++)
{
scheds[n] = new MemSched[cmax];
for (int i = 0; i < cmax; i++)
{
scheds[n][i] = Activator.CreateInstance(Config.sched.typeof_sched_algo) as MemSched;
}
}
MemSched[][] wbscheds = new MemSched[Config.mem.mctrl_num][];
for (int n = 0; n < Config.mem.mctrl_num; n++)
{
wbscheds[n] = new MemSched[cmax];
if (!Config.sched.same_sched_algo)
{
for (int i = 0; i < cmax; i++)
{
wbscheds[n][i] = Activator.CreateInstance(Config.sched.typeof_wbsched_algo) as MemSched;
}
}
else
{
for (int i = 0; i < cmax; i++)
{
wbscheds[n][i] = scheds[n][i];
}
}
}
MetaMemCtrl[][] meta_mctrls = new MetaMemCtrl[Config.mem.mctrl_num][];
for (int n = 0; n < Config.mem.mctrl_num; n++)
{
meta_mctrls[n] = new MetaMemCtrl[cmax];
for (int i = 0; i < cmax; i++)
{
meta_mctrls[n][i] = new MetaMemCtrl(mctrls[n][i], scheds[n][i], wbscheds[n][i]);
mctrls[n][i].meta_mctrl = meta_mctrls[n][i];
scheds[n][i].meta_mctrl = meta_mctrls[n][i];
scheds[n][i].initialize();
wbscheds[n][i].meta_mctrl = meta_mctrls[n][i];
wbscheds[n][i].initialize();
}
}
}
else
{
MemSched[] sched = new MemSched[Config.mem.mctrl_num];
MemSched[] wbsched = new MemSched[Config.mem.mctrl_num];
for (int n = 0; n < Config.mem.mctrl_num; n++)
{
sched[n] = Activator.CreateInstance(Config.sched.typeof_sched_algo) as MemSched;
if (!Config.sched.same_sched_algo)
{
wbsched[n] = Activator.CreateInstance(Config.sched.typeof_wbsched_algo) as MemSched;
}
else
{
wbsched[n] = sched[n];
}
}
MetaMemCtrl[] meta_mctrl = new MetaMemCtrl[Config.mem.mctrl_num];
for (int n = 0; n < Config.mem.mctrl_num; n++)
{
meta_mctrl[n] = new MetaMemCtrl(mctrls[n], sched[n], wbsched[n]);
for (int i = 0; i < cmax; i++)
{
mctrls[n][i].meta_mctrl = meta_mctrl[n];
}
sched[n].meta_mctrl = meta_mctrl[n];
sched[n].initialize();
wbsched[n].meta_mctrl = meta_mctrl[n];
wbsched[n].initialize();
}
}
//wbmode
for (int n = 0; n < Config.mem.mctrl_num; n++)
{
mwbmode = Activator.CreateInstance(Config.mctrl.typeof_wbmode_algo, new Object[] { mctrls[n] }) as MemWBMode;
for (int i = 0; i < cmax; i++)
{
mctrls[n][i].mwbmode = mwbmode;
}
//blp tracker
blptracker = new BLPTracker(mctrls[n]);
}
}
public OrCoupledDynamicWindow(MemCtrl[] mctrls)
: base(mctrls)
{
window = Config.mctrl.wb_window;
}
protected bool is_writeq_empty(uint cid)
{
MemCtrl mctrl = mctrls[cid];
return(mctrl.wload == 0);
}
public List <Req> get_readq(Bank bank)
{
MemCtrl mc = get_mctrl(bank);
return(mc.readqs[bank.rid, bank.bid]);
}
public List <Req> get_writeq(Bank bank)
{
MemCtrl mc = get_mctrl(bank);
return(mc.writeqs[bank.rid, bank.bid]);
}
public override void tick(uint cid)
{
if (cid != 0)
{
return;
}
cycles++;
//check for end of wb_mode
for (uint i = 0; i < cmax; i++)
{
if (!wb_mode[i])
{
continue;
}
MemCtrl mctrl = mctrls[i];
int wb_marked_cnt = 0;
foreach (Req req in mctrl.mctrl_writeq)
{
if (req.wb_marked)
{
wb_marked_cnt++;
}
}
if (wb_marked_cnt > (1 - drain_fraction) * mctrl.mctrl_writeq.Capacity)
{
continue;
}
foreach (Req req in mctrl.mctrl_writeq)
{
req.wb_marked = false;
}
wb_mode[i] = false;
}
//check for start of wb_mode
for (uint i = 0; i < cmax; i++)
{
if (wb_mode[i])
{
continue;
}
if (!is_writeq_full(i))
{
continue;
}
MemCtrl mctrl = mctrls[i];
foreach (Req req in mctrl.mctrl_writeq)
{
Dbg.Assert(!req.wb_marked);
req.wb_marked = true;
}
wb_mode[i] = true;
}
}
public RowHitFinder(MemCtrl mctrl)
{
this.mctrl = mctrl;
}