public static void initialize()
{
DDR3DRAM ddr3_temp1 = new DDR3DRAM(Config.mem.ddr3_type, Config.mem.clock_factor, 0, 0);
DDR3DRAM ddr3_temp2 = new DDR3DRAM(Config.mem2.ddr3_type, Config.mem2.clock_factor, 0, 0);
diff_read_cost = ddr3_temp1.timing.tRCD - ddr3_temp2.timing.tRCD;
diff_write_cost = ddr3_temp1.timing.tWR - ddr3_temp2.timing.tWR;
// for(int i=0; i<Config.N ; i++)
// r[i] = 1;
Interval = Row_Migration_Policies.Interval;
prev_core_stall_cycles = new ulong[Config.N];
// prev_core_rpkc = new ulong[Config.N];
// prev_core_wpkc = new ulong[Config.N];
prev_interference = new double[Config.N];
prev_memtime = new ulong[Config.N];
for (int i = 0; i < Config.N; i++)
{
prev_core_stall_cycles[i] = 0;
// prev_core_rpkc[i] = 0;
// prev_core_wpkc[i] = 0;
prev_interference[i] = 0;
prev_memtime[i] = 0;
}
ThreadWeight = new double [Config.N];
for (int i = 0; i < Config.N; i++)
{
ThreadWeight[i] = 1;
}
// migration_cost = 8*1024/64;
// eff_thresh = 8*1024/64 * 8/2 * 0.5;
}
//constructor
public MemCtrl(uint rmax, DDR3DRAM ddr3)
{
this.cid = cmax;
cmax++;
//states
this.rmax = rmax;
this.bmax = ddr3.BANK_MAX;
//DDR3
timing = ddr3.timing;
this.col_max = ddr3.COL_MAX;
this.row_size = ddr3.COL_MAX * ddr3.CHANNEL_WIDTH;
//components
chan = new Channel(this, rmax, ddr3.BANK_MAX);
//row-hit finder
rh_finder = new RowHitFinder(this);
//queues
int readq_max = Config.mctrl.readq_max_per_bank;
writeq_max = (int)this.rmax * (int)this.bmax * Config.mctrl.writeq_max_per_bank;
readqs = new List <Req> [rmax, bmax];
writeqs = new List <Req> [rmax, bmax];
mctrl_writeq = new List <Req>(writeq_max);
inflightqs = new List <Req> [rmax, bmax];
cmdqs = new List <Cmd> [rmax, bmax];
for (uint r = 0; r < rmax; r++)
{
for (uint b = 0; b < bmax; b++)
{
readqs[r, b] = new List <Req>(readq_max);
writeqs[r, b] = new List <Req>(writeq_max);
inflightqs[r, b] = new List <Req>(INFLIGHTQ_MAX);
cmdqs[r, b] = new List <Cmd>(CMDQ_MAX);
}
}
bus_q = new List <BusTransaction>((int)BUS_TRANSACTIONS_MAX);
//stats
rload_per_proc = new uint[Config.N];
rload_per_procrankbank = new uint[Config.N, rmax, bmax];
shadow_rowid_per_procrankbank = new ulong[Config.N, rmax, bmax];
rowid_per_procrankbank = new ulong[rmax, bmax];
pid_rowid_per_procrankbank = new int[rmax, bmax];
wload_per_proc = new uint[Config.N];
wload_per_procrankbank = new uint[Config.N, rmax, bmax];
//writeback throttler
wbthrottle = Activator.CreateInstance(Config.sched.typeof_wbthrottle_algo) as WBThrottle;
total_queueing_latency = new ulong[Config.N];
curr_proc = new int[bmax];
}
//constructor
public MemCtrl(uint rmax, DDR3DRAM ddr3)
{
this.cid = cmax;
cmax++;
//states
this.rmax = rmax;
this.bmax = ddr3.BANK_MAX;
//DDR3
timing = ddr3.timing;
this.col_max = ddr3.COL_MAX;
this.row_size = ddr3.COL_MAX * ddr3.CHANNEL_WIDTH;
//components
chan = new Channel(this, rmax, ddr3.BANK_MAX);
//row-hit finder
rh_finder = new RowHitFinder(this);
//queues
int readq_max = Config.mctrl.readq_max_per_bank;
writeq_max = (int)this.rmax * (int)this.bmax * Config.mctrl.writeq_max_per_bank;
readqs = new List<Req>[rmax, bmax];
writeqs = new List<Req>[rmax, bmax];
mctrl_writeq = new List<Req>(writeq_max);
inflightqs = new List<Req>[rmax, bmax];
cmdqs = new List<Cmd>[rmax, bmax];
for (uint r = 0; r < rmax; r++) {
for (uint b = 0; b < bmax; b++) {
readqs[r, b] = new List<Req>(readq_max);
writeqs[r, b] = new List<Req>(writeq_max);
inflightqs[r, b] = new List<Req>(INFLIGHTQ_MAX);
cmdqs[r, b] = new List<Cmd>(CMDQ_MAX);
}
}
bus_q = new List<BusTransaction>((int)BUS_TRANSACTIONS_MAX);
//stats
rload_per_proc = new uint[Config.N];
rload_per_procrankbank = new uint[Config.N, rmax, bmax];
shadow_rowid_per_procrankbank = new ulong[Config.N, rmax, bmax];
rowid_per_procrankbank = new ulong[rmax, bmax];
wload_per_proc = new uint[Config.N];
wload_per_procrankbank = new uint[Config.N, rmax, bmax];
//writeback throttler
wbthrottle = Activator.CreateInstance(Config.sched.typeof_wbthrottle_algo) as WBThrottle;
total_queueing_latency = new ulong[Config.N];
curr_proc = new int[bmax];
}
//ratio of write miss cost and read miss cost used for comparing with MissTresh
// static ulong ExpectedDramReadMiss;
// static ulong ExpectedDramWriteMiss;
public static void initialize()
{
DDR3DRAM ddr3_temp1 = new DDR3DRAM(Config.mem.ddr3_type, Config.mem.clock_factor, 0, 0);
DDR3DRAM ddr3_temp2 = new DDR3DRAM(Config.mem2.ddr3_type, Config.mem2.clock_factor, 0, 0);
migration_cost = (ulong)Config.mem.clock_factor * ddr3_temp1.COL_MAX * (ulong)(1 << Config.proc.block_size_bits) / ddr3_temp1.CHANNEL_WIDTH * 8 / 2; //8: byte size; 2: each edge transfers one data
diff_read_cost = ddr3_temp1.timing.tRCD - ddr3_temp2.timing.tRCD;
diff_write_cost = ddr3_temp1.timing.tWR - ddr3_temp2.timing.tWR;
weight = diff_write_cost / diff_read_cost;
if ((migration_cost <= 0) || (diff_read_cost <= 0) || (diff_write_cost <= 0) || (weight <= 0))
{
Console.WriteLine("RBLA Big Mistake");
}
MissThresh = migration_cost / diff_read_cost;
}
//constructor
public static void init(MapEnum map_type, uint channel_max, uint rank_max, uint col_per_subrow, DDR3DRAM ddr3)
{
MemMap.map_type = map_type;
MemMap.channel_max = channel_max;
//bits
chan_bits = (uint)Math.Log(channel_max, 2);
rank_bits = (uint)Math.Log(rank_max, 2);
bank_bits = (uint)Math.Log(ddr3.BANK_MAX, 2);
col_bits = (uint)Math.Log(ddr3.COL_MAX, 2);
if (col_per_subrow > 0) {
col2_bits = (uint)Math.Log(col_per_subrow, 2);
col1_bits = col_bits - col2_bits;
}
else {
col2_bits = 0;
}
transfer_bits = (uint)Math.Log(64, 2); //64B transfer
//mask, offset
set_maskoffset();
}
static void initialize()
{
if (Config.task_based == true)
{
string task_fname = Config.traceFileNames[0];
if (Config.sim_type == Config.SIM_TYPE.GROUPED)
{
task_fname = Config.traceFileNames[Config.group_boundary];
}
foreach (string dir in Config.TraceDirs.Split(',', ' '))
{
if (File.Exists(dir + "/" + task_fname))
{
task_fname = dir + "/" + task_fname;
}
}
Dbg.Assert(File.Exists(task_fname));
StreamReader tasks = new StreamReader(File.OpenRead(task_fname));
while (true)
{
string line = tasks.ReadLine();
if (line == null)
{
break;
}
task_queue.Enqueue(line);
}
tasks.Close();
}
Dram_Utilization_size = 0;
Dram_req_num = 0;
NVM_req_num = 0;
//randomized page table
ulong page_size = 4 * 1024;
PageRandomizer prand = new PageRandomizer(page_size);
Req.prand = prand;
//processors
procs = new Proc[Config.N];
for (int p = 0; p < Config.N; p++)
{
if ((Config.task_based == true && Config.sim_type != Config.SIM_TYPE.GROUPED) ||
(Config.task_based == true && Config.sim_type == Config.SIM_TYPE.GROUPED && p >= Config.group_boundary && p < Config.N))
{
procs[p] = new Proc(task_queue.Dequeue());
}
else
{
procs[p] = new Proc(Config.traceFileNames[p]);
}
}
//crossbar
xbar = new Xbar();
// warmup phase
proc_warmup = new bool[Config.N];
proc_warmup_cycles = new ulong[Config.N];
for (int p = 0; p < Config.N; p++)
{
proc_warmup[p] = false;
proc_warmup_cycles[p] = 0;
}
// Power Measurement:
processor_finished = new bool[Config.N];
DRAM_processor_read_hit = new ulong[Config.N];
DRAM_processor_read_miss = new ulong[Config.N];
DRAM_processor_write_hit = new ulong[Config.N];
DRAM_processor_write_miss = new ulong[Config.N];
DRAM_migration_read_hit = new ulong[Config.N];
DRAM_migration_read_miss = new ulong[Config.N];
DRAM_migration_write_hit = new ulong[Config.N];
DRAM_migration_write_miss = new ulong[Config.N];
NVM_processor_read_hit = new ulong[Config.N];
NVM_processor_read_miss = new ulong[Config.N];
NVM_processor_write_hit = new ulong[Config.N];
NVM_processor_write_miss = new ulong[Config.N];
NVM_migration_read_hit = new ulong[Config.N];
NVM_migration_read_miss = new ulong[Config.N];
NVM_migration_write_hit = new ulong[Config.N];
NVM_migration_write_miss = new ulong[Config.N];
processor_cycles = new ulong[Config.N];
for (int p = 0; p < Config.N; p++)
{
processor_finished[p] = false;
DRAM_processor_read_hit[p] = 0;
DRAM_processor_read_miss[p] = 0;
DRAM_processor_write_hit[p] = 0;
DRAM_processor_write_miss[p] = 0;
DRAM_migration_read_hit[p] = 0;
DRAM_migration_read_miss[p] = 0;
DRAM_migration_write_hit[p] = 0;
DRAM_migration_write_miss[p] = 0;
NVM_processor_read_hit[p] = 0;
NVM_processor_read_miss[p] = 0;
NVM_processor_write_hit[p] = 0;
NVM_processor_write_miss[p] = 0;
NVM_migration_read_hit[p] = 0;
NVM_migration_read_miss[p] = 0;
NVM_migration_write_hit[p] = 0;
NVM_migration_write_miss[p] = 0;
processor_cycles[p] = 0;
}
//
//Jin: Row Migration Policies
rmp = new Row_Migration_Policies();
mesur = new Measurement();
//ddr3
DDR3DRAM ddr3 = new DDR3DRAM(Config.mem.ddr3_type, Config.mem.clock_factor, Config.mem.tWR, Config.mem.tWTR);
uint cmax = (uint)Config.mem.channel_max;
uint rmax = (uint)Config.mem.rank_max;
//sequential page table
PageSequencer pseq = new PageSequencer(page_size, cmax, rmax, ddr3.BANK_MAX);
Req.pseq = pseq;
//memory mapping
MemMap.init(Config.mem.map_type, Config.mem.channel_max, Config.mem.rank_max, Config.mem.col_per_subrow, ddr3);
//memory controllers
mctrls = new MemCtrl[Config.mem.mctrl_num][];
for (int n = 0; n < Config.mem.mctrl_num; n++)
{
mctrls[n] = new MemCtrl[cmax];
for (int i = 0; i < mctrls[n].Length; i++)
{
mctrls[n][i] = new MemCtrl(rmax, ddr3);
}
}
//memory schedulers and metamemory controllers
if (!Config.sched.is_omniscient)
{
MemSched[][] scheds = new MemSched[Config.mem.mctrl_num][];
for (int n = 0; n < Config.mem.mctrl_num; n++)
{
scheds[n] = new MemSched[cmax];
for (int i = 0; i < cmax; i++)
{
scheds[n][i] = Activator.CreateInstance(Config.sched.typeof_sched_algo) as MemSched;
}
}
MemSched[][] wbscheds = new MemSched[Config.mem.mctrl_num][];
for (int n = 0; n < Config.mem.mctrl_num; n++)
{
wbscheds[n] = new MemSched[cmax];
if (!Config.sched.same_sched_algo)
{
for (int i = 0; i < cmax; i++)
{
wbscheds[n][i] = Activator.CreateInstance(Config.sched.typeof_wbsched_algo) as MemSched;
}
}
else
{
for (int i = 0; i < cmax; i++)
{
wbscheds[n][i] = scheds[n][i];
}
}
}
MetaMemCtrl[][] meta_mctrls = new MetaMemCtrl[Config.mem.mctrl_num][];
for (int n = 0; n < Config.mem.mctrl_num; n++)
{
meta_mctrls[n] = new MetaMemCtrl[cmax];
for (int i = 0; i < cmax; i++)
{
meta_mctrls[n][i] = new MetaMemCtrl(mctrls[n][i], scheds[n][i], wbscheds[n][i]);
mctrls[n][i].meta_mctrl = meta_mctrls[n][i];
scheds[n][i].meta_mctrl = meta_mctrls[n][i];
scheds[n][i].initialize();
wbscheds[n][i].meta_mctrl = meta_mctrls[n][i];
wbscheds[n][i].initialize();
}
}
}
else
{
MemSched[] sched = new MemSched[Config.mem.mctrl_num];
MemSched[] wbsched = new MemSched[Config.mem.mctrl_num];
for (int n = 0; n < Config.mem.mctrl_num; n++)
{
sched[n] = Activator.CreateInstance(Config.sched.typeof_sched_algo) as MemSched;
if (!Config.sched.same_sched_algo)
{
wbsched[n] = Activator.CreateInstance(Config.sched.typeof_wbsched_algo) as MemSched;
}
else
{
wbsched[n] = sched[n];
}
}
MetaMemCtrl[] meta_mctrl = new MetaMemCtrl[Config.mem.mctrl_num];
for (int n = 0; n < Config.mem.mctrl_num; n++)
{
meta_mctrl[n] = new MetaMemCtrl(mctrls[n], sched[n], wbsched[n]);
for (int i = 0; i < cmax; i++)
{
mctrls[n][i].meta_mctrl = meta_mctrl[n];
}
sched[n].meta_mctrl = meta_mctrl[n];
sched[n].initialize();
wbsched[n].meta_mctrl = meta_mctrl[n];
wbsched[n].initialize();
}
}
//wbmode
for (int n = 0; n < Config.mem.mctrl_num; n++)
{
mwbmode = Activator.CreateInstance(Config.mctrl.typeof_wbmode_algo, new Object[] { mctrls[n] }) as MemWBMode;
for (int i = 0; i < cmax; i++)
{
mctrls[n][i].mwbmode = mwbmode;
}
//blp tracker
blptracker = new BLPTracker(mctrls[n]);
}
}
static void initialize()
{
//processors
//crossbar
xbar = new Xbar();
//ddr3
DDR3DRAM ddr3 = new DDR3DRAM(Config.mem.ddr3_type, Config.mem.clock_factor, Config.mem.tWR, Config.mem.tWTR);
uint cmax = (uint)Config.mem.channel_max;
uint rmax = (uint)Config.mem.rank_max;
//randomized page table
ulong page_size = 4 * 1024;
PageRandomizer prand = new PageRandomizer(page_size);
Req.prand = prand;
Console.Write("Initializing prand\n");
//sequential page table
PageSequencer pseq = new PageSequencer(page_size, cmax, rmax, ddr3.BANK_MAX);
Req.pseq = pseq;
if (Config.is_shared_cache)
{
Console.Write("Initializing shared cache\n");
shared_cache = new Cache();
}
else
{
Console.Write("Initializing private cache\n");
shared_cache = null;
}
procs = new Proc[Config.N];
for (int p = 0; p < Config.N; p++)
{
if (shared_cache == null)
{
procs[p] = new Proc(new Cache(), new L1Cache(), Config.traceFileNames[p]);
}
else
{
Console.Write("Shared\n");
procs[p] = new Proc(shared_cache, new L1Cache(), Config.traceFileNames[p]);
}
}
Console.Write(" periodic dump " + Config.periodic_dump + "\n");
if (Config.periodic_dump)
{
rep_name_periodic_ipc = Config.periodic_name + "_ipc_periodic.txt";
Console.Write("Creating IPC periodic file\n");
periodic_writer_ipc = File.CreateText(rep_name_periodic_ipc);
}
//memory mapping
MemMap.init(Config.mem.map_type, Config.mem.channel_max, Config.mem.rank_max, Config.mem.col_per_subrow, ddr3);
//memory controllers
mctrls = new MemCtrl[cmax];
for (int i = 0; i < mctrls.Length; i++)
{
mctrls[i] = new MemCtrl(rmax, ddr3);
}
//memory schedulers and metamemory controllers
if (!Config.sched.is_omniscient)
{
MemSched[] scheds = new MemSched[cmax];
for (int i = 0; i < cmax; i++)
{
scheds[i] = Activator.CreateInstance(Config.sched.typeof_sched_algo) as MemSched;
}
MemSched[] wbscheds = new MemSched[cmax];
if (!Config.sched.same_sched_algo)
{
for (int i = 0; i < cmax; i++)
{
wbscheds[i] = Activator.CreateInstance(Config.sched.typeof_wbsched_algo) as MemSched;
}
}
else
{
for (int i = 0; i < cmax; i++)
{
wbscheds[i] = scheds[i];
}
}
MetaMemCtrl[] meta_mctrls = new MetaMemCtrl[cmax];
for (int i = 0; i < cmax; i++)
{
meta_mctrls[i] = new MetaMemCtrl(mctrls[i], scheds[i], wbscheds[i]);
mctrls[i].meta_mctrl = meta_mctrls[i];
scheds[i].meta_mctrl = meta_mctrls[i];
scheds[i].initialize();
wbscheds[i].meta_mctrl = meta_mctrls[i];
wbscheds[i].initialize();
}
}
else
{
MemSched sched = Activator.CreateInstance(Config.sched.typeof_sched_algo) as MemSched;
MemSched wbsched;
if (!Config.sched.same_sched_algo)
{
wbsched = Activator.CreateInstance(Config.sched.typeof_wbsched_algo) as MemSched;
}
else
{
wbsched = sched;
}
MetaMemCtrl meta_mctrl = new MetaMemCtrl(mctrls, sched, wbsched);
for (int i = 0; i < cmax; i++)
{
mctrls[i].meta_mctrl = meta_mctrl;
}
sched.meta_mctrl = meta_mctrl;
sched.initialize();
wbsched.meta_mctrl = meta_mctrl;
wbsched.initialize();
}
//wbmode
mwbmode = Activator.CreateInstance(Config.mctrl.typeof_wbmode_algo, new Object[] { mctrls }) as MemWBMode;
for (int i = 0; i < cmax; i++)
{
mctrls[i].mwbmode = mwbmode;
}
//blp tracker
blptracker = new BLPTracker(mctrls);
}
//constructor
public static void init(MapEnum map_type, uint channel_max, uint rank_max, uint col_per_subrow, DDR3DRAM ddr3)
{
MemMap.map_type = map_type;
MemMap.channel_max = channel_max;
//bits
chan_bits = (uint)Math.Log(channel_max, 2);
rank_bits = (uint)Math.Log(rank_max, 2);
bank_bits = (uint)Math.Log(ddr3.BANK_MAX, 2);
col_bits = (uint)Math.Log(ddr3.COL_MAX, 2);
if (col_per_subrow > 0)
{
col2_bits = (uint)Math.Log(col_per_subrow, 2);
col1_bits = col_bits - col2_bits;
}
else
{
col2_bits = 0;
}
transfer_bits = (uint)Math.Log(64, 2); //64B transfer
//mask, offset
set_maskoffset();
}
public Measurement()
{
mem_read_num = new int[Config.N];
mem_write_num = new int[Config.N];
for (int i = 0; i < Config.N; i++)
{
mem_read_num[i] = 0;
mem_write_num[i] = 0;
}
Dram_bus_conflict = new bool[Config.N];
NVM_bus_conflict = new bool[Config.N];
for (int i = 0; i < Config.N; i++)
{
Dram_bus_conflict[i] = false;
NVM_bus_conflict[i] = false;
}
interference = new double[Config.N];
interference_Acc = new double[Config.N];
memtime = new ulong[Config.N];
memtime_Acc = new ulong[Config.N];
for (int i = 0; i < Config.N; i++)
{
interference[i] = 0;
interference_Acc[i] = 0;
memtime[i] = 0;
memtime_Acc[i] = 0;
}
// MLP_rd_bank_num = new int[Config.N];
// MLP_wr_bank_num = new int[Config.N];
core_stall_cycles = new ulong[Config.N];
warmup_core_stall_cycles = new ulong[Config.N];
core_rpkc = new ulong[Config.N];
core_wpkc = new ulong[Config.N];
for (int i = 0; i < Config.N; i++)
{
// MLP_rd_bank_num[i] = 0;
// MLP_wr_bank_num[i] = 0;
core_stall_cycles[i] = 0;
warmup_core_stall_cycles[i] = 0;
core_rpkc[i] = 0;
core_wpkc[i] = 0;
}
DDR3DRAM ddr2 = new DDR3DRAM(Config.mem2.ddr3_type, Config.mem2.clock_factor, Config.mem2.tWR, Config.mem2.tWTR);
DDR3DRAM ddr = new DDR3DRAM(Config.mem.ddr3_type, Config.mem.clock_factor, Config.mem.tWR, Config.mem.tWTR);
Dram_Q_rd_miss = (double)(ddr2.timing.tRTP + ddr2.timing.tRP + ddr2.timing.tRCD + ddr2.timing.tBL);
Dram_Q_wr_miss = (double)(ddr2.timing.tWR + ddr2.timing.tRP + ddr2.timing.tRCD + ddr2.timing.tBL);
Dram_Q_rd_hit = (double)(ddr2.timing.tCL + ddr2.timing.tBL);
Dram_Q_wr_hit = (double)(ddr2.timing.tCL + ddr2.timing.tBL);
NVM_Q_rd_miss = (double)(ddr.timing.tRTP + ddr.timing.tRP + ddr.timing.tRCD + ddr.timing.tBL);
NVM_Q_wr_miss = (double)(ddr.timing.tWR + ddr.timing.tRP + ddr.timing.tRCD + ddr.timing.tBL);
NVM_Q_rd_hit = (double)(ddr.timing.tCL + ddr.timing.tBL);
NVM_Q_wr_hit = (double)(ddr.timing.tCL + ddr.timing.tBL);
Dram_rowbufferunit = (long)((ddr2.timing.tRP + ddr2.timing.tRCD) / Config.mem.clock_factor);
NVM_rowbufferunit = (long)((ddr.timing.tRP + ddr.timing.tRCD) / Config.mem.clock_factor);
Dram_Q_rd_miss_init = Dram_Q_rd_miss;
Dram_Q_wr_miss_init = Dram_Q_wr_miss;
Dram_Q_rd_hit_init = Dram_Q_rd_hit;
Dram_Q_wr_hit_init = Dram_Q_wr_hit;
NVM_Q_rd_miss_init = NVM_Q_rd_miss;
NVM_Q_wr_miss_init = NVM_Q_wr_miss;
NVM_Q_rd_hit_init = NVM_Q_rd_hit;
NVM_Q_wr_hit_init = NVM_Q_wr_hit;
/* Dram_Q_rd_miss_Acc = 0;
* Dram_Q_wr_miss_Acc = 0;
* Dram_Q_rd_hit_Acc = 0;
* Dram_Q_wr_miss_Acc = 0;
* NVM_Q_rd_miss_Acc = 0;
* NVM_Q_wr_miss_Acc = 0;
* NVM_Q_rd_hit_Acc = 0;
* NVM_Q_wr_hit_Acc = 0;
*
* Dram_Q_rd_miss_times = 0;
* Dram_Q_wr_miss_times = 0;
* Dram_Q_rd_hit_times = 0;
* Dram_Q_wr_miss_times = 0;
* NVM_Q_rd_miss_times = 0;
* NVM_Q_wr_miss_times = 0;
* NVM_Q_rd_hit_times = 0;
* NVM_Q_wr_hit_times = 0;
*
*/
Dram_bank_num = (int)(Config.mem2.channel_max * Config.mem2.rank_max * ddr2.BANK_MAX);
NVM_bank_num = (int)(Config.mem.channel_max * Config.mem.rank_max * ddr.BANK_MAX);
Dram_BANK_MAX = (int)ddr2.BANK_MAX;
NVM_BANK_MAX = (int)ddr.BANK_MAX;
core_stall = new bool[Config.N];
bank_conflict = new bool[Config.N];
t_excess = new double[Config.N];
t_excess_Acc = new double[Config.N];
// t_excess_total = new double[Config.N];
core_req_num = new int[Config.N, Dram_bank_num + NVM_bank_num];
// core_rd_req_num = new int[Config.N, Dram_bank_num + NVM_bank_num];
// core_wr_req_num = new int[Config.N, Dram_bank_num + NVM_bank_num];
bank_req_pid = new int[Dram_bank_num + NVM_bank_num];
rowbuffer_change = new long[Config.N, Dram_bank_num + NVM_bank_num];
core_prev_rowid = new ulong[Config.N, Dram_bank_num + NVM_bank_num];
for (int i = 0; i < Config.N; i++)
{
core_stall[i] = false;
bank_conflict[i] = false;
t_excess[i] = 0;
t_excess_Acc[i] = 0;
// t_excess_total[i] = 0;
for (int j = 0; j < Dram_bank_num + NVM_bank_num; j++)
{
core_req_num[i, j] = 0;
rowbuffer_change[i, j] = 0;
// core_rd_req_num[i,j] = 0;
// core_wr_req_num[i,j] = 0;
bank_req_pid[j] = Config.N;
core_prev_rowid[i, j] = 0;
}
}
}
static void initialize()
{
//processors
//crossbar
xbar = new Xbar();
//ddr3
DDR3DRAM ddr3 = new DDR3DRAM(Config.mem.ddr3_type, Config.mem.clock_factor, Config.mem.tWR, Config.mem.tWTR);
uint cmax = (uint)Config.mem.channel_max;
uint rmax = (uint)Config.mem.rank_max;
//randomized page table
ulong page_size = 4 * 1024;
PageRandomizer prand = new PageRandomizer(page_size);
Req.prand = prand;
Console.Write("Initializing prand\n");
//sequential page table
PageSequencer pseq = new PageSequencer(page_size, cmax, rmax, ddr3.BANK_MAX);
Req.pseq = pseq;
if (Config.is_shared_cache)
{
Console.Write("Initializing shared cache\n");
shared_cache = new Cache();
}
else
{
Console.Write("Initializing private cache\n");
shared_cache = null;
}
procs = new Proc[Config.N];
for (int p = 0; p < Config.N; p++) {
if (shared_cache == null)
procs[p] = new Proc(new Cache(), new L1Cache(), Config.traceFileNames[p]);
else
{
Console.Write("Shared\n");
procs[p] = new Proc(shared_cache, new L1Cache(), Config.traceFileNames[p]);
}
}
Console.Write(" periodic dump " + Config.periodic_dump + "\n");
if (Config.periodic_dump)
{
rep_name_periodic_ipc = Config.periodic_name + "_ipc_periodic.txt";
Console.Write("Creating IPC periodic file\n");
periodic_writer_ipc = File.CreateText(rep_name_periodic_ipc);
}
//memory mapping
MemMap.init(Config.mem.map_type, Config.mem.channel_max, Config.mem.rank_max, Config.mem.col_per_subrow, ddr3);
//memory controllers
mctrls = new MemCtrl[cmax];
for (int i = 0; i < mctrls.Length; i++) {
mctrls[i] = new MemCtrl(rmax, ddr3);
}
//memory schedulers and metamemory controllers
if (!Config.sched.is_omniscient) {
MemSched[] scheds = new MemSched[cmax];
for (int i = 0; i < cmax; i++) {
scheds[i] = Activator.CreateInstance(Config.sched.typeof_sched_algo) as MemSched;
}
MemSched[] wbscheds = new MemSched[cmax];
if (!Config.sched.same_sched_algo) {
for (int i = 0; i < cmax; i++) {
wbscheds[i] = Activator.CreateInstance(Config.sched.typeof_wbsched_algo) as MemSched;
}
}
else {
for (int i = 0; i < cmax; i++) {
wbscheds[i] = scheds[i];
}
}
MetaMemCtrl[] meta_mctrls = new MetaMemCtrl[cmax];
for (int i = 0; i < cmax; i++) {
meta_mctrls[i] = new MetaMemCtrl(mctrls[i], scheds[i], wbscheds[i]);
mctrls[i].meta_mctrl = meta_mctrls[i];
scheds[i].meta_mctrl = meta_mctrls[i];
scheds[i].initialize();
wbscheds[i].meta_mctrl = meta_mctrls[i];
wbscheds[i].initialize();
}
}
else {
MemSched sched = Activator.CreateInstance(Config.sched.typeof_sched_algo) as MemSched;
MemSched wbsched;
if (!Config.sched.same_sched_algo) {
wbsched = Activator.CreateInstance(Config.sched.typeof_wbsched_algo) as MemSched;
}
else {
wbsched = sched;
}
MetaMemCtrl meta_mctrl = new MetaMemCtrl(mctrls, sched, wbsched);
for (int i = 0; i < cmax; i++) {
mctrls[i].meta_mctrl = meta_mctrl;
}
sched.meta_mctrl = meta_mctrl;
sched.initialize();
wbsched.meta_mctrl = meta_mctrl;
wbsched.initialize();
}
//wbmode
mwbmode = Activator.CreateInstance(Config.mctrl.typeof_wbmode_algo, new Object[] { mctrls }) as MemWBMode;
for (int i = 0; i < cmax; i++) {
mctrls[i].mwbmode = mwbmode;
}
//blp tracker
blptracker = new BLPTracker(mctrls);
}
public DRAMTrueLRU()
{
this.sets = Config.proc.cache_sets;
this.ways = Config.proc.cache_ways;
this.latency = Config.proc.cache_latency;
data = new TagEntry[sets][];
reqs = new Queue <Req>();
wbs = new Queue <Req>();
DDR3DRAM ddr3 = new DDR3DRAM(Config.mem2.ddr3_type, Config.mem2.clock_factor, Config.mem2.tWR, Config.mem2.tWTR);
uint cmax = (uint)Config.mem2.channel_max;
uint rmax = (uint)Config.mem2.rank_max;
//memory controllers
mctrls2 = new MemCtrl2[Config.mem2.mctrl_num][];
for (int n = 0; n < Config.mem2.mctrl_num; n++)
{
mctrls2[n] = new MemCtrl2[cmax];
for (int i = 0; i < mctrls2[n].Length; i++)
{
mctrls2[n][i] = new MemCtrl2(rmax, ddr3);
}
}
//memory schedulers and metamemory controllers
if (!Config.sched.is_omniscient)
{
MemSched2[][] scheds = new MemSched2[Config.mem2.mctrl_num][];
for (int n = 0; n < Config.mem2.mctrl_num; n++)
{
scheds[n] = new MemSched2[cmax];
for (int i = 0; i < cmax; i++)
{
scheds[n][i] = Activator.CreateInstance(Config.sched.typeof_sched_algo2) as MemSched2;
}
}
MemSched2[][] wbscheds = new MemSched2[Config.mem2.mctrl_num][];
for (int n = 0; n < Config.mem2.mctrl_num; n++)
{
wbscheds[n] = new MemSched2[cmax];
if (!Config.sched.same_sched_algo)
{
for (int i = 0; i < cmax; i++)
{
wbscheds[n][i] = Activator.CreateInstance(Config.sched.typeof_wbsched_algo2) as MemSched2;
}
}
else
{
for (int i = 0; i < cmax; i++)
{
wbscheds[n][i] = scheds[n][i];
}
}
}
MetaMemCtrl2[][] meta_mctrls2 = new MetaMemCtrl2[Config.mem2.mctrl_num][];
for (int n = 0; n < Config.mem2.mctrl_num; n++)
{
meta_mctrls2[n] = new MetaMemCtrl2[cmax];
for (int i = 0; i < cmax; i++)
{
meta_mctrls2[n][i] = new MetaMemCtrl2(mctrls2[n][i], scheds[n][i], wbscheds[n][i]);
mctrls2[n][i].meta_mctrl = meta_mctrls2[n][i];
scheds[n][i].meta_mctrl = meta_mctrls2[n][i];
scheds[n][i].initialize();
wbscheds[n][i].meta_mctrl = meta_mctrls2[n][i];
wbscheds[n][i].initialize();
}
}
}
else
{
MemSched2[] sched = new MemSched2[Config.mem2.mctrl_num];
MemSched2[] wbsched = new MemSched2[Config.mem2.mctrl_num];
for (int n = 0; n < Config.mem2.mctrl_num; n++)
{
sched[n] = Activator.CreateInstance(Config.sched.typeof_sched_algo2) as MemSched2;
if (!Config.sched.same_sched_algo)
{
wbsched[n] = Activator.CreateInstance(Config.sched.typeof_wbsched_algo2) as MemSched2;
}
else
{
wbsched[n] = sched[n];
}
}
MetaMemCtrl2[] meta_mctrl = new MetaMemCtrl2[Config.mem2.mctrl_num];
for (int n = 0; n < Config.mem2.mctrl_num; n++)
{
meta_mctrl[n] = new MetaMemCtrl2(mctrls2[n], sched[n], wbsched[n]);
for (int i = 0; i < cmax; i++)
{
mctrls2[n][i].meta_mctrl = meta_mctrl[n];
}
sched[n].meta_mctrl = meta_mctrl[n];
sched[n].initialize();
wbsched[n].meta_mctrl = meta_mctrl[n];
wbsched[n].initialize();
}
}
//wbmode
for (int n = 0; n < Config.mem2.mctrl_num; n++)
{
Console.WriteLine(Config.mctrl.typeof_wbmode_algo);
mwbmode = Activator.CreateInstance(Config.mctrl.typeof_wbmode_algo2, new Object[] { mctrls2[n] }) as MemWBMode2;
for (int i = 0; i < cmax; i++)
{
mctrls2[n][i].mwbmode = mwbmode;
}
//blp tracker
blptracker = new BLPTracker2(mctrls2[n]);
}
for (int set = 0; set < sets; set++)
{
data[set] = new TagEntry[ways];
for (int way = 0; way < ways; way++)
{
data[set][way] = new TagEntry();
data[set][way].valid = false;
data[set][way].addr = 0x0;
data[set][way].access = 0;
// data[set][way].dirty = false;
data[set][way].pid = -1;
data[set][way].block_valid = new bool[Config.proc.page_block_diff];
data[set][way].block_dirty = new bool[Config.proc.page_block_diff];
for (int block_id = 0; block_id < Config.proc.page_block_diff; block_id++)
{
data[set][way].block_valid[block_id] = false;
data[set][way].block_dirty[block_id] = false;
}
}
}
}
