void reqDone(ulong addr, int mshr, bool write)
{
m_ins.setReady(addr, write);
// if(m_is_HWA && ( m_ID == 17 ))
// if(( m_ID == 0 ) || ( m_ID == 17 ))
// Console.WriteLine("{1}-Lat:{0}", Simulator.CurrentRound - m_mshrs[mshr].reqTime,m_ID );
if (!m_is_GPU)
{
if (!write && m_mshrs[mshr].pending_write)
{
m_mshrs[mshr].pending_write = false;
m_mshrs[mshr].write = true;
/* HWA CODE */
// _issueReq(mshr, m_mshrs[mshr].block << Config.cache_block, true, Simulator.CurrentRound);
_issueReq(mshr, m_mshrs[mshr].block << Config.cache_block, true, Simulator.CurrentRound, 0);
/* HWA CODE END */
}
else
{
/*
* ulong myAddr = m_mshrs[mshr].addr;
* ulong myReqTime = m_mshrs[mshr].reqTime;
* bool myl2m;
* if (addr_l2m.ContainsKey(myAddr))
* {
* myl2m = (bool) addr_l2m[myAddr];
* addr_l2m.Remove(myAddr);
* }
* else
* throw new Exception(String.Format("unable to find the L2 status in the hashtable {0}.", myAddr));
*
*
* if (myl2m == false)
* {
* //Simulator.stats.L2_potential_MLP[m_ID].Add();
* for (int i = 0; i < m_mshrs.Length; i++)
* {
* if (m_mshrs[i].valid && i != mshr)
* {
* if (m_mshrs[i].reqTime < myReqTime)
* {
* //Simulator.stats.L2_potential_MLP[m_ID].Add();
* break;
* }
* }
* }
* }*/
m_mshrs[mshr].valid = false;
m_mshrs[mshr].block = 0;
m_mshrs[mshr].write = false;
m_mshrs[mshr].pending_write = false;
mshrs_free++;
}
}
}
void reqDone(ulong addr, int mshr, bool write)
{
m_ins.setReady(addr, write);
// if (m_ID == 0) Console.WriteLine("P0 finish req block {0:X} write {1} at cyc {2}, hit {3}", addr>>Config.cache_block, write, Simulator.CurrentRound, write, !l1miss);
if (!write && m_mshrs[mshr].pending_write)
{
m_mshrs[mshr].pending_write = false;
m_mshrs[mshr].write = true;
_issueReq(mshr, m_mshrs[mshr].block << Config.cache_block, true);
}
else
{
m_mshrs[mshr].valid = false;
m_mshrs[mshr].block = 0;
m_mshrs[mshr].write = false;
m_mshrs[mshr].pending_write = false;
mshrs_free++;
}
}