protected override void DoCommandAction()
{
ReadVivadoFPGADebugger.AddWireRegex(
WireRegexType,
WireRegex_StartTile,
WireRegex_StartPort,
WireRegex_EndTile,
WireRegex_EndPort);
}
private void ProcessWires(string line, StreamReader sr, ref long currentcharCount, long totalCharCount)
{
string currentTileName = "";
Tile currentTile = null;
WireList wl = new WireList();
string wireLine = line;
WireHelper wireHelper = new WireHelper();
do
{
currentcharCount += wireLine.Length;
if (PrintProgress)
{
ProgressInfo.Progress = (int)(((double)currentcharCount / (double)totalCharCount) * (ExcludePipsToBidirectionalWiresFromBlocking ? 50 : 100));
}
if (m_commentRegexp.IsMatch(wireLine))
{
Console.WriteLine(wireLine);
continue;
}
int equalIndex = wireLine.IndexOf('=');
int sepIndex = wireLine.IndexOf('>', equalIndex);
string left = wireLine.Substring(equalIndex + 1, sepIndex - equalIndex - 2);
int slashIndexLeft = left.IndexOf("/");
string fromTile = left.Substring(0, slashIndexLeft);
string fromPip = left.Substring(slashIndexLeft + 1);//, left.Length - slashIndexLeft-1);
if (string.IsNullOrEmpty(currentTileName))
{
currentTileName = fromTile;
currentTile = FPGA.FPGA.Instance.GetTile(currentTileName);
}
else if (!fromTile.Equals(currentTileName))
{
if (currentTile.WireList != null)
{
throw new ArgumentException("Wirelist should be null");
}
XDLTileParser.StoreAndShareWireList(currentTile, wl);
currentTileName = fromTile;
currentTile = FPGA.FPGA.Instance.GetTile(currentTileName);
wl = new WireList();
}
string right = wireLine.Substring(sepIndex + 1);//, wireLine.Length - sepIndex - 1);
int slashIndexRight = right.IndexOf("/");
string toTile = right.Substring(0, slashIndexRight);
string toPip = right.Substring(slashIndexRight + 1);//, right.Length - slashIndexRight - 1);
Tile tile = FPGA.FPGA.Instance.GetTile(fromTile);
Tile target = FPGA.FPGA.Instance.GetTile(toTile);
uint localPipKey = FPGA.FPGA.Instance.IdentifierListLookup.GetKey(fromPip);
if (WireHelper.GetIncludeFlag(WireHelper.IncludeFlag.WiresTrajectoriesData))
{
tile.AddWireTrajectoryData(localPipKey, FPGA.FPGA.Instance.IdentifierListLookup.GetKey(toTile));
}
if (!currentTile.SwitchMatrix.Contains(fromPip))
{
if (!WireHelper.GetIncludeFlag(WireHelper.IncludeFlag.BELOutWires) ||
!wireHelper.IsBELOutPip(currentTile, fromPip))
{
ReadVivadoFPGADebugger.DebugWire(fromTile, fromPip, toTile, toPip);
continue;
}
}
short xIncr = (short)(target.TileKey.X - currentTile.TileKey.X);
short yIncr = (short)(target.TileKey.Y - currentTile.TileKey.Y);
// Check if we should consider U-turn wires
bool condition = WireHelper.GetIncludeFlag(WireHelper.IncludeFlag.UTurnWires);
condition = condition ? fromTile != toTile || fromPip != toPip : xIncr != 0 || yIncr != 0;
if (!condition)
{
ReadVivadoFPGADebugger.DebugWire(fromTile, fromPip, toTile, toPip);
continue;
}
if (!target.SwitchMatrix.Contains(toPip))
{
if (!WireHelper.GetIncludeFlag(WireHelper.IncludeFlag.BELInWires) ||
!wireHelper.IsBELInPip(target, toPip))
{
ReadVivadoFPGADebugger.DebugWire(fromTile, fromPip, toTile, toPip);
continue;
}
}
uint pipOnOtherTileKey = FPGA.FPGA.Instance.IdentifierListLookup.GetKey(toPip);
Port from = new Port(fromPip);
//Port to = new Port(toPip);
bool fromIsBegin = currentTile.SwitchMatrix.ContainsRight(from);
Wire w = new Wire(localPipKey, pipOnOtherTileKey, fromIsBegin, xIncr, yIncr);
wl.Add(w);
if (WireHelper.GetIncludeFlag(WireHelper.IncludeFlag.IncomingWires))
{
target.AddIncomingWire(w);
}
}while ((wireLine = sr.ReadLine()) != null);
wireHelper.ProcessStopoverArcs();
}
protected override void DoCommandAction()
{
// reset PRIOR to reading to reset high lighter
CommandExecuter.Instance.Execute(new Reset());
FPGA.FPGA.Instance.Reset();
FPGA.FPGA.Instance.BackendType = FPGATypes.BackendType.Vivado;
// create reader & open file
StreamReader sr = new StreamReader(FileName);
FileInfo fi = new FileInfo(FileName);
long charCount = 0;
long lineCount = 0;
string line = "";
while ((line = sr.ReadLine()) != null)
{
lineCount++;
charCount += line.Length;
if (PrintProgress)
{
ProgressInfo.Progress = (int)(((double)charCount / (double)fi.Length) * (ExcludePipsToBidirectionalWiresFromBlocking ? 50 : 100));
}
if (m_commentRegexp.IsMatch(line))
{
continue;
}
int length = line.IndexOf('=');
string prefix = line.Substring(0, length);
switch (prefix)
{
case "Device":
Watch.Start("ProcessDevice");
ProcessDevice(line);
Watch.Stop("ProcessDevice");
break;
case "R":
Watch.Start("ProcessTile");
ProcessTile(line);
Watch.Stop("ProcessTile");
break;
case "Site":
Watch.Start("ProcessSite");
ProcessSite(line);
Watch.Stop("ProcessSite");
break;
case "Pips":
Watch.Start("ProcessPips");
ProcessPips(line);
Watch.Stop("ProcessPips");
break;
case "Wire":
Watch.Start("ProcessWire");
ProcessWires(line, sr, ref charCount, fi.Length);
Watch.Stop("ProcessWire");
break;
default:
{
throw new ArgumentException("Unknown line type: " + line + " (line" + lineCount + ")");
}
}
}
sr.Close();
ReadVivadoFPGADebugger.CloseStream();
WireList emptyWl = new WireList();
foreach (Tile tile in FPGA.FPGA.Instance.GetAllTiles().Where(t => t.WireList == null))
{
XDLTileParser.StoreAndShareWireList(tile, emptyWl);
}
if (ExcludePipsToBidirectionalWiresFromBlocking)
{
ExcludePipsToBidirectionalWiresFromBlocking exclCmd = new ExcludePipsToBidirectionalWiresFromBlocking();
exclCmd.Profile = Profile;
exclCmd.PrintProgress = PrintProgress;
exclCmd.ProgressStart = 50;
exclCmd.ProgressShare = 50;
exclCmd.FileName = "";
CommandExecuter.Instance.Execute(exclCmd);
}
CommandExecuter.Instance.Execute(new Reset());
// no LoadFPGAFamilyScript here! LoadFPGAFamilyScript is called through Reset
// remember for other stuff how we read in this FPGA
Blackboard.Instance.LastLoadCommandForFPGA = ToString();
}
protected override void DoCommandAction()
{
ReadVivadoFPGADebugger.ResetWireRegexes();
}
protected override void DoCommandAction()
{
ReadVivadoFPGADebugger.DisableAndReset();
}