public static void WriteData(uint baud, FPGA.OutputSignal <bool> TXD, ComplexFloat[] data, uint duration) { bool internalTXD = true; FPGA.Config.Link(internalTXD, TXD); FPGA.SyncStream <uint> streamWriter = new FPGA.SyncStream <uint>(); Sequential <uint> streamHandler = (d) => { UART.RegisteredWriteUnsigned32(baud, d, out internalTXD); }; FPGA.Config.OnStream(streamWriter, streamHandler); ComplexFloat tmp = new ComplexFloat(); uint uns = 0; for (uint i = 0; i < data.Length; i++) { FPGA.Config.SetInclusiveRange(0, data.Length, i); tmp = data[i]; for (byte idx = 0; idx < 2; idx++) { FPGA.Config.SetInclusiveRange(0, 2, idx); switch (idx) { case 0: FPGA.Runtime.Assign(FPGA.Expressions.Unchecked(tmp.Re, out uns)); break; case 1: FPGA.Runtime.Assign(FPGA.Expressions.Unchecked(tmp.Im, out uns)); break; } streamWriter.Write(uns); } } streamWriter.Write(duration); }
public static async Task Aggregator( FPGA.InputSignal <bool> RXD, FPGA.OutputSignal <bool> TXD ) { const int baud = 115200; uint clockCounter = 0; Diag.ClockCounter(clockCounter); bool internalTXD = true; FPGA.Config.Link(internalTXD, TXD); byte testOp; float op1, op2, res = 0; Sequential handler = () => { FPU.FPUScope(); while (true) { uint start = 0, end = 0; res = 0; UART.Read(baud, RXD, out testOp); UART.ReadFloat(baud, RXD, out op1); UART.ReadFloat(baud, RXD, out op2); switch ((FPUTimingType)testOp) { case FPUTimingType.Add: start = clockCounter; res = op1 + op2; end = clockCounter; break; case FPUTimingType.Sub: start = clockCounter; res = op1 - op2; end = clockCounter; break; case FPUTimingType.Mul: start = clockCounter; res = op1 * op2; end = clockCounter; break; case FPUTimingType.Div: start = clockCounter; res = op1 / op2; end = clockCounter; break; default: start = clockCounter; end = clockCounter; break; } UART.RegisteredWriteFloat(baud, res, out internalTXD); UART.RegisteredWriteUnsigned32(baud, end - start, out internalTXD); } }; FPGA.Config.OnStartup(handler); }