void EmulateCyclesWith1541()
{
thread_running = true;
while (!quit_thyself)
{
// The order of calls is important here
if (TheVIC.EmulateCycle())
{
TheSID.EmulateLine();
}
TheCIA1.CheckIRQs();
TheCIA2.CheckIRQs();
TheCIA1.EmulateCycle();
TheCIA2.EmulateCycle();
TheCPU.EmulateCycle();
TheCPU1541.CountVIATimers(1);
if (!TheCPU1541.Idle)
{
TheCPU1541.EmulateCycle();
}
CycleCounter++;
}
}
void write_byte_io(UInt16 adr, byte abyte)
{
if (adr >= 0xe000)
{
ram[adr] = abyte;
if (adr == 0xff00)
{
TheREU.FF00Trigger();
}
}
else if (io_in)
{
switch ((adr >> 8) & 0x0f)
{
case 0x0: // VIC
case 0x1:
case 0x2:
case 0x3:
TheVIC.WriteRegister((UInt16)(adr & 0x3f), abyte);
return;
case 0x4: // SID
case 0x5:
case 0x6:
case 0x7:
TheSID.WriteRegister((UInt16)(adr & 0x1f), abyte);
return;
case 0x8: // Color RAM
case 0x9:
case 0xa:
case 0xb:
color_ram[adr & 0x03ff] = (byte)(abyte & 0x0f);
return;
case 0xc: // CIA 1
TheCIA1.WriteRegister((UInt16)(adr & 0x0f), abyte);
return;
case 0xd: // CIA 2
TheCIA2.WriteRegister((UInt16)(adr & 0x0f), abyte);
return;
case 0xe: // REU/Open I/O
case 0xf:
if ((adr & 0xfff0) == 0xdf00)
{
TheREU.WriteRegister((UInt16)(adr & 0x0f), abyte);
}
return;
}
}
else
{
ram[adr] = abyte;
}
}
void EmulateCyclesWithout1541()
{
#if TIMERS
uint lc = CycleCounter;
HiResTimer timer = new HiResTimer();
timer.Start();
const uint cycleCount = 4000000;
#endif
thread_running = true;
while (!quit_thyself)
{
// The order of calls is important here
if (TheVIC.EmulateCycle())
{
TheSID.EmulateLine();
}
TheCIA1.CheckIRQs();
TheCIA2.CheckIRQs();
TheCIA1.EmulateCycle();
TheCIA2.EmulateCycle();
TheCPU.EmulateCycle();
CycleCounter++;
#if TIMERS
if (CycleCounter - lc == cycleCount)
{
timer.Stop();
lc = CycleCounter;
double elapsedSec = timer.ElapsedMilliseconds / 1000.0f;
Console.WriteLine("------------------------------------");
Console.WriteLine("{0} ms elapsed for {1:N} cycles", timer.ElapsedMilliseconds, cycleCount);
Console.WriteLine("CIA1: TA Interrupts: {0} -> int/s: {1}", TheCIA1.ta_interrupts, TheCIA1.ta_interrupts / elapsedSec);
Console.WriteLine("CPU Instructions: {0} -> ins/s: {1}", TheCPU.ins_counter, TheCPU.ins_counter / elapsedSec);
// reset counters
TheCIA1.ta_interrupts = 0;
TheCIA1.tb_interrupts = 0;
TheCIA2.ta_interrupts = 0;
TheCIA2.tb_interrupts = 0;
TheCPU.ins_counter = 0;
timer.Reset();
timer.Start();
//TheDisplay.Surface.Update();
}
#endif
}
}
byte read_byte_io(UInt16 adr)
{
switch (adr >> 12)
{
case 0xa:
case 0xb:
if (basic_in)
{
return(basic_rom[adr & 0x1fff]);
}
else
{
return(ram[adr]);
}
case 0xc:
return(ram[adr]);
case 0xd:
if (io_in)
{
switch ((adr >> 8) & 0x0f)
{
case 0x0: // VIC
case 0x1:
case 0x2:
case 0x3:
return(TheVIC.ReadRegister((UInt16)(adr & 0x3f)));
case 0x4: // SID
case 0x5:
case 0x6:
case 0x7:
return(TheSID.ReadRegister((UInt16)(adr & 0x1f)));
case 0x8: // Color RAM
case 0x9:
case 0xa:
case 0xb:
return((byte)(color_ram[adr & 0x03ff] & 0x0f | TheVIC.LastVICByte & 0xf0));
case 0xc: // CIA 1
return(TheCIA1.ReadRegister((UInt16)(adr & 0x0f)));
case 0xd: // CIA 2
return(TheCIA2.ReadRegister((UInt16)(adr & 0x0f)));
case 0xe: // REU/Open I/O
case 0xf:
if ((adr & 0xfff0) == 0xdf00)
{
return(TheREU.ReadRegister((UInt16)(adr & 0x0f)));
}
else if (adr < 0xdfa0)
{
return(TheVIC.LastVICByte);
}
else
{
return(read_emulator_id((UInt16)(adr & 0x7f)));
}
}
}
else if (char_in)
{
return(char_rom[adr & 0x0fff]);
}
return(ram[adr]);
case 0xe:
case 0xf:
if (kernal_in)
{
return(kernel_rom[adr & 0x1fff]);
}
else
{
return(ram[adr]);
}
default: // Can't happen
return(0);
}
}
