public List <SignalDefenition> ParseSignals(string vhdl)
{
var signalSection = Regex.Match(vhdl, signalSectionPattern).Value;
List <SignalDefenition> signals = new List <SignalDefenition>();
MatchesToStrings(Regex.Matches(signalSection, SignalPattern)).ForEach(x =>
{
Match pTypeMatch = Regex.Match(x, PortType);
var remainngWithValueType = x.Substring(pTypeMatch.Index + pTypeMatch.Length);
var defaultPart = Regex.Match(remainngWithValueType, Default).Value;
var portEnumeration = Regex.Match(remainngWithValueType, Enumeration).Value;
var newSignal = new SignalDefenition(Document.Entity)
{
Name = Regex.Match(x, PortName).Value,
ValueType = pTypeMatch.Value,
DefaultValue = defaultPart != String.Empty ? Regex.Match(defaultPart, DefaultValue).Value : null,
Enumeration = !String.IsNullOrWhiteSpace(portEnumeration) ? EnumerationParser.Parse(portEnumeration) : null
};
signals.Add(newSignal);
});
return(signals);
}
public static AssignmentSide Create(Assignment assignment, SignalDefenition defenition, EnumerationBase enumeration = null)
{
var result = new AssignmentSide(assignment, defenition.ToString());
result.Signal = assignment.Document.Router.AssignmentSignal(result, defenition);
return(result);
}
public SignalDefenition GetEquivalent(SignalDefenition signal)
{
if (IsBuffered(signal))
{
return(Equivalents[signal]);
}
return(null);
}
public static Assignment Create(Map map, Port left, SignalDefenition right, EnumerationBase enumeration = null)
{
var result = new Assignment()
{
Map = map,
Text = left + " => " + right + ","
};
result._left = AssignmentSide.Create(result, left);
result._rigt = AssignmentSide.Create(result, right, enumeration);
if (!result.Validation())
{
throw new Exception("Inncorect bits");
}
return(result);
}
public void Parse()
{
var buffers = new List <IOBuffer>();
var ioBuffers =
Document.Maps.Where(buf => buf.Name.Contains("IBUF"))
.Select(map => IOBuffer.Extract(map, false)).ToList();
ioBuffers.AddRange(Document.Maps.Where(buf => buf.Name.Contains("OBUF"))
.Select(map => IOBuffer.Extract(map, true)));
buffers.AddRange(ioBuffers);
buffers.GroupBy(x => x.OutsideSignal.Defenition, y => y).ToList().ForEach(o =>
{
if (o.Count() == 1)
{
Equivalents.Add(o.Key, o.Single().InsideSignal.Defenition);
}
else
{
var signalForInject = new SignalDefenition(Document.Entity)
{
Name = o.Key.Name + Helper.NewGuidName(),
Enumeration = o.Key.Enumeration.Clone() as EnumerationBase,
ValueType = o.Key.ValueType
};
Document.Router.InserSignalDefenition(signalForInject);
o.ToList().ForEach(b =>
{
Document.Router.Replace(b.InsideSignal.Defenition, signalForInject, b.OutsideSignal.Enumeration?.CloneEnumeration());
//Document.Router.NewRout(newPeaceOfWire, innside);
});
Equivalents.Add(o.Key, signalForInject);
}
}
);
}
public static AssignmentSignal Parse(ISignalsParentSection parent, string text, SignalDefenition defaultDefenition = null)
{
var signalStr = Regex.Match(text, PC.VHDLName + PC.MFS + PC.Enumeration).Value;
var name = Regex.Match(signalStr, PC.VHDLName).Value;
name = string.IsNullOrEmpty(name) ? Regex.Match(text, ParsConstants.VHDLName).Value : name;
EnumerationBase enumeration = null;
if (!String.IsNullOrEmpty(signalStr))
{
var enumerationStr = Regex.Match(signalStr, PC.Enumeration).Value;
enumeration = EnumerationParser.Parse(enumerationStr);
if (enumeration == null)
{
return(null);
}
}
var isComponentPort = false;
bool?isSource = null;
var defenition = defaultDefenition ?? parent.Document.Signals.GetSignalDefenition(name);
if (defenition == null)
{
//Error unknown signal
defenition = parent.Document.Entity.Ports.FirstOrDefault(x => x.Name == name);
if (defenition == null)
{
var component = parent.Document.Components
.FirstOrDefault(x => x.Name == parent.EntityName);
if (component != null)
{
defenition = component.Ports.FirstOrDefault(f => f.Name == name);
}
else
{
defenition = new Port(null)
{
Name = name, PortType = PortTypes.In
}; //TODO Delete
}
}
isComponentPort = true;
isSource = (defenition as Port).PortType != PortTypes.In;
}
return(new AssignmentSignal(defenition, parent)
{
Name = Regex.Match(text, ParsConstants.VHDLName).Value,
IsComponentPort = isComponentPort,
IsSource = isSource,
Enumeration = enumeration
});
}
public AssignmentSignal(SignalDefenition defenition, ISignalsParentSection parent)
{
Defenition = defenition;
SignalsParentSection = parent;
}
public SignalDefenition WhetherEquivalent(SignalDefenition signal)
{
return(IsBuffered(signal) ? Equivalents[signal] : signal);
}
public bool IsBuffered(SignalDefenition signal)
{
return(Equivalents.ContainsKey(signal));
}
public OutWatermarkSettings(SignalDefenition signal)
{
Signal = signal;
}
public PartialSignal(AssignmentSide parent, SignalDefenition defenition, EnumerationBase enumeration) : base(defenition, parent)
{
Name = defenition.Name;
Enumeration = enumeration;
}