public byte GetReg(RegWD1793 reg, ulong tact)
{
this.process(tact);
switch (reg)
{
case RegWD1793.COMMAND:
this.rqs &= (BETA_STATUS)127;
return((byte)this.status);
case RegWD1793.TRACK:
return(this.track);
case RegWD1793.SECTOR:
return(this.sector);
case RegWD1793.DATA:
this.status &= ~WD_STATUS.WDS_INDEX;
this.rqs &= (BETA_STATUS)191;
return(this.data);
case RegWD1793.BETA128:
return((byte)(this.rqs | (BETA_STATUS)63));
default:
throw new Exception("WD1793.GetReg: Invalid register");
}
}
public void SetReg(RegWD1793 reg, byte value, ulong tact)
{
this.process(tact);
switch (reg)
{
case RegWD1793.COMMAND:
if ((value & 240) == 208)
{
this.state = WDSTATE.S_IDLE;
this.rqs = BETA_STATUS.INTRQ;
this.status &= ~WD_STATUS.WDS_BUSY;
}
else if ((this.status & WD_STATUS.WDS_BUSY) == (WD_STATUS)0)
{
this.cmd = value;
this.next = tact;
this.status |= WD_STATUS.WDS_BUSY;
this.rqs = BETA_STATUS.NONE;
if ((this.cmd & 128) != 0)
{
if ((this.status & WD_STATUS.WDS_NOTRDY) != (WD_STATUS)0)
{
this.state = WDSTATE.S_IDLE;
this.rqs = BETA_STATUS.INTRQ;
}
else
{
if (this.fdd[this.drive].motor > 0UL || this.wd93_nodelay)
{
this.fdd[this.drive].motor = this.next + 7000000UL;
}
this.state = WDSTATE.S_DELAY_BEFORE_CMD;
}
}
else
{
this.state = WDSTATE.S_TYPE1_CMD;
}
}
break;
case RegWD1793.TRACK:
this.track = value;
break;
case RegWD1793.SECTOR:
this.sector = value;
break;
case RegWD1793.DATA:
this.data = value;
this.rqs &= (BETA_STATUS)191;
this.status &= ~WD_STATUS.WDS_INDEX;
break;
case RegWD1793.BETA128:
this.system = value;
this.drive = (int)(value & 3);
this.side = (1 & ~(value >> 4));
this.fdd[this.drive & 3].HeadSide = this.side;
this.trkcache = this.fdd[this.drive & 3].CurrentTrack;
if ((value & 4) == 0)
{
this.status = WD_STATUS.WDS_NOTRDY;
this.rqs = BETA_STATUS.INTRQ;
this.fdd[this.drive].motor = 0UL;
this.state = WDSTATE.S_IDLE;
}
break;
default:
throw new Exception("WD1793.SetReg: Invalid register");
}
this.process(tact);
}
