// Conventions:
// - All temporary registers are float4s.
// - Scalar ops swizzle out a single component of their source registers denoted
// by 'a' or 'b'. src0.a means 'the first component specified for src0' and
// src0.ab means 'two components specified for src0, in order'.
// - Scalar ops write the result to the entire destination register.
// - pv and ps are the previous results of a vector or scalar ALU operation.
// Both are valid only within the current ALU clause. They are not modified
// when write masks are disabled or the instruction that would write them
// fails its predication check.
// Translates an ALU Vector/Scalar pair into HLSL fragments (Vector and Scalar ALU instructions
// are ALWAYS executed in pairs, and are part of the same instruction definition.
public static void Get(Instruction instruction)
{
PreFixups.Apply(ref instruction.alu_instr);
if (instruction.alu_instr.Has_vector_op)
{
Vector(instruction);
}
if (instruction.alu_instr.Has_scalar_op)
{
Scalar(instruction);
}
}
// Translates a VFetch or TFetch type instruction into an HLSL fragment.
public static string Get(Instruction instruction)
{
PreFixups.Apply(ref instruction.fetch_instr);
string translation = "";
if (instruction.fetch_instr.opcode == FetchOpCode.vfetch)
{
translation += Vfetch(instruction);
}
else
{
translation += Tfetch(instruction);
}
return(translation);
}