/// <summary>
/// Generates assembly source.
///
/// This code is common to all generators.
/// </summary>
/// <param name="gen">Reference to generator object (presumably the caller).</param>
/// <param name="sw">Text output sink.</param>
/// <param name="worker">Background worker object, for progress updates and
/// cancelation requests.</param>
public static void Generate(IGenerator gen, StreamWriter sw, BackgroundWorker worker)
{
DisasmProject proj = gen.Project;
Formatter formatter = gen.SourceFormatter;
int offset = 0;
bool doAddCycles = gen.Settings.GetBool(AppSettings.SRCGEN_SHOW_CYCLE_COUNTS, false);
LocalVariableLookup lvLookup = new LocalVariableLookup(proj.LvTables, proj,
gen.Localizer.LabelMap, gen.Quirks.LeadingUnderscoreSpecial,
gen.Quirks.NoRedefinableSymbols);
GenerateHeader(gen, sw);
// Used for M/X flag tracking.
StatusFlags prevFlags = StatusFlags.AllIndeterminate;
int lastProgress = 0;
while (offset < proj.FileData.Length)
{
Anattrib attr = proj.GetAnattrib(offset);
if (attr.IsInstructionStart && offset > 0 &&
proj.GetAnattrib(offset - 1).IsData)
{
// Transition from data to code. (Don't add blank line for inline data.)
gen.OutputLine(string.Empty);
}
// Long comments come first.
if (proj.LongComments.TryGetValue(offset, out MultiLineComment longComment))
{
List <string> formatted = longComment.FormatText(formatter, string.Empty);
foreach (string str in formatted)
{
gen.OutputLine(str);
}
}
// Check for address change.
int orgAddr = proj.AddrMap.Get(offset);
if (orgAddr >= 0)
{
gen.OutputOrgDirective(offset, orgAddr);
}
List <DefSymbol> lvars = lvLookup.GetVariablesDefinedAtOffset(offset);
if (lvars != null)
{
// table defined here
gen.OutputLocalVariableTable(offset, lvars,
lvLookup.GetMergedTableAtOffset(offset));
}
if (attr.IsInstructionStart)
{
// Generate M/X reg width directive, if necessary.
// NOTE: we can suppress the initial directive if we know what the
// target assembler's default assumption is. Probably want to handle
// that in the ORG output handler.
if (proj.CpuDef.HasEmuFlag)
{
StatusFlags curFlags = attr.StatusFlags;
curFlags.M = attr.StatusFlags.ShortM ? 1 : 0;
curFlags.X = attr.StatusFlags.ShortX ? 1 : 0;
if (curFlags.M != prevFlags.M || curFlags.X != prevFlags.X)
{
// changed, output directive
gen.OutputRegWidthDirective(offset, prevFlags.M, prevFlags.X,
curFlags.M, curFlags.X);
}
prevFlags = curFlags;
}
// Look for embedded instructions.
int len;
for (len = 1; len < attr.Length; len++)
{
if (proj.GetAnattrib(offset + len).IsInstructionStart)
{
break;
}
}
// Output instruction.
GenerateInstruction(gen, sw, lvLookup, offset, len, doAddCycles);
if (attr.DoesNotContinue)
{
gen.OutputLine(string.Empty);
}
offset += len;
}
else
{
gen.OutputDataOp(offset);
offset += attr.Length;
}
// Update progress meter. We don't want to spam it, so just ping it 10x.
int curProgress = (offset * 10) / proj.FileData.Length;
if (lastProgress != curProgress)
{
if (worker.CancellationPending)
{
Debug.WriteLine("GenCommon got cancellation request");
return;
}
lastProgress = curProgress;
worker.ReportProgress(curProgress * 10);
//System.Threading.Thread.Sleep(500);
}
}
}
/// <summary>
/// Generates assembly source.
///
/// This code is common to all generators.
/// </summary>
/// <param name="gen">Reference to generator object (presumably the caller).</param>
/// <param name="sw">Text output sink.</param>
/// <param name="worker">Background worker object, for progress updates and
/// cancelation requests.</param>
public static void Generate(IGenerator gen, StreamWriter sw, BackgroundWorker worker)
{
DisasmProject proj = gen.Project;
Formatter formatter = gen.SourceFormatter;
int offset = gen.StartOffset;
bool doAddCycles = gen.Settings.GetBool(AppSettings.SRCGEN_SHOW_CYCLE_COUNTS, false);
LocalVariableLookup lvLookup = new LocalVariableLookup(proj.LvTables, proj,
gen.Localizer.LabelMap, gen.Quirks.LeadingUnderscoreSpecial,
gen.Quirks.NoRedefinableSymbols);
GenerateHeader(gen, sw);
// Used for M/X flag tracking.
StatusFlags prevFlags = StatusFlags.AllIndeterminate;
int lastProgress = 0;
// Create an address map iterator and advance it to match gen.StartOffset.
IEnumerator <AddressMap.AddressChange> addrIter = proj.AddrMap.AddressChangeIterator;
while (addrIter.MoveNext())
{
if (addrIter.Current.IsStart && addrIter.Current.Offset >= offset)
{
break;
}
}
bool arDirectPending = false;
while (offset < proj.FileData.Length)
{
Anattrib attr = proj.GetAnattrib(offset);
if (attr.IsInstructionStart && offset > 0 &&
proj.GetAnattrib(offset - 1).IsData)
{
// Transition from data to code. (Don't add blank line for inline data.)
gen.OutputLine(string.Empty);
}
// Long comments come first.
if (proj.LongComments.TryGetValue(offset, out MultiLineComment longComment))
{
List <string> formatted = longComment.FormatText(formatter, string.Empty);
foreach (string str in formatted)
{
gen.OutputLine(str);
}
}
// Check for address range starts. There may be more than one at a given offset.
AddressMap.AddressChange change = addrIter.Current;
while (change != null && change.Offset == offset)
{
if (change.IsStart)
{
gen.OutputArDirective(change);
arDirectPending = true;
addrIter.MoveNext();
change = addrIter.Current;
}
else
{
break;
}
}
// Reached end of start directives. Write the last one.
if (arDirectPending)
{
gen.FlushArDirectives();
arDirectPending = false;
}
List <DefSymbol> lvars = lvLookup.GetVariablesDefinedAtOffset(offset);
if (lvars != null)
{
// table defined here
gen.OutputLocalVariableTable(offset, lvars,
lvLookup.GetMergedTableAtOffset(offset));
}
if (attr.IsInstructionStart)
{
// Generate M/X reg width directive, if necessary.
// NOTE: we can suppress the initial directive if we know what the
// target assembler's default assumption is. Probably want to handle
// that in the ORG output handler.
if (proj.CpuDef.HasEmuFlag)
{
StatusFlags curFlags = attr.StatusFlags;
curFlags.M = attr.StatusFlags.IsShortM ? 1 : 0;
curFlags.X = attr.StatusFlags.IsShortX ? 1 : 0;
if (curFlags.M != prevFlags.M || curFlags.X != prevFlags.X)
{
// changed, output directive
gen.OutputRegWidthDirective(offset, prevFlags.M, prevFlags.X,
curFlags.M, curFlags.X);
}
prevFlags = curFlags;
}
// Look for embedded instructions.
int len;
for (len = 1; len < attr.Length; len++)
{
if (proj.GetAnattrib(offset + len).IsInstructionStart)
{
break;
}
}
// Output instruction.
GenerateInstruction(gen, sw, lvLookup, offset, len, doAddCycles);
if (attr.DoesNotContinue)
{
gen.OutputLine(string.Empty);
}
offset += len;
}
else
{
gen.OutputDataOp(offset);
offset += attr.Length;
}
// Check for address region ends. There may be more than one at a given offset.
// The end-region offset will be the last byte of the instruction or data item,
// so it should be one less than the updated offset.
//
// If we encounter a region start, we'll handle that at the top of the next
// loop iteration.
while (change != null && change.Offset + 1 == offset)
{
if (!change.IsStart)
{
gen.OutputArDirective(change);
arDirectPending = true;
addrIter.MoveNext();
change = addrIter.Current;
}
else
{
break;
}
}
// Update progress meter. We don't want to spam it, so just ping it 10x.
int curProgress = (offset * 10) / proj.FileData.Length;
if (lastProgress != curProgress)
{
if (worker.CancellationPending)
{
Debug.WriteLine("GenCommon got cancellation request");
return;
}
lastProgress = curProgress;
worker.ReportProgress(curProgress * 10);
//System.Threading.Thread.Sleep(500);
}
}
Debug.Assert(offset == proj.FileDataLength);
}
private static void GenerateInstruction(IGenerator gen, StreamWriter sw,
LocalVariableLookup lvLookup, int offset, int instrBytes, bool doAddCycles)
{
DisasmProject proj = gen.Project;
Formatter formatter = gen.SourceFormatter;
byte[] data = proj.FileData;
Anattrib attr = proj.GetAnattrib(offset);
string labelStr = string.Empty;
if (attr.Symbol != null)
{
labelStr = gen.Localizer.ConvLabel(attr.Symbol.Label);
}
OpDef op = proj.CpuDef.GetOpDef(data[offset]);
int operand = op.GetOperand(data, offset, attr.StatusFlags);
int instrLen = op.GetLength(attr.StatusFlags);
OpDef.WidthDisambiguation wdis = OpDef.WidthDisambiguation.None;
if (op.IsWidthPotentiallyAmbiguous)
{
wdis = OpDef.GetWidthDisambiguation(instrLen, operand);
}
if (gen.Quirks.SinglePassAssembler && wdis == OpDef.WidthDisambiguation.None &&
(op.AddrMode == OpDef.AddressMode.DP ||
op.AddrMode == OpDef.AddressMode.DPIndexX) ||
op.AddrMode == OpDef.AddressMode.DPIndexY)
{
// Could be a forward reference to a direct-page label. For ACME, we don't
// care if it's forward or not.
if ((gen.Quirks.SinglePassNoLabelCorrection && IsLabelReference(gen, offset)) ||
IsForwardLabelReference(gen, offset))
{
wdis = OpDef.WidthDisambiguation.ForceDirect;
}
}
string opcodeStr = formatter.FormatOpcode(op, wdis);
string formattedOperand = null;
int operandLen = instrLen - 1;
PseudoOp.FormatNumericOpFlags opFlags = PseudoOp.FormatNumericOpFlags.OmitLabelPrefixSuffix;
bool isPcRelBankWrap = false;
// Tweak branch instructions. We want to show the absolute address rather
// than the relative offset (which happens with the OperandAddress assignment
// below), and 1-byte branches should always appear as a 4-byte hex value.
if (op.AddrMode == OpDef.AddressMode.PCRel)
{
Debug.Assert(attr.OperandAddress >= 0);
operandLen = 2;
opFlags |= PseudoOp.FormatNumericOpFlags.IsPcRel;
}
else if (op.AddrMode == OpDef.AddressMode.PCRelLong ||
op.AddrMode == OpDef.AddressMode.StackPCRelLong)
{
opFlags |= PseudoOp.FormatNumericOpFlags.IsPcRel;
}
else if (op.AddrMode == OpDef.AddressMode.Imm ||
op.AddrMode == OpDef.AddressMode.ImmLongA ||
op.AddrMode == OpDef.AddressMode.ImmLongXY)
{
opFlags |= PseudoOp.FormatNumericOpFlags.HasHashPrefix;
}
if ((opFlags & PseudoOp.FormatNumericOpFlags.IsPcRel) != 0)
{
int branchDist = attr.Address - attr.OperandAddress;
isPcRelBankWrap = branchDist > 32767 || branchDist < -32768;
}
// 16-bit operands outside bank 0 need to include the bank when computing
// symbol adjustment.
int operandForSymbol = operand;
if (attr.OperandAddress >= 0)
{
operandForSymbol = attr.OperandAddress;
}
// Check Length to watch for bogus descriptors. (ApplyFormatDescriptors() should
// now be screening bad descriptors out, so we may not need the Length test.)
if (attr.DataDescriptor != null && attr.Length == attr.DataDescriptor.Length)
{
FormatDescriptor dfd = gen.ModifyInstructionOperandFormat(offset,
attr.DataDescriptor, operand);
// Format operand as directed.
if (op.AddrMode == OpDef.AddressMode.BlockMove)
{
// Special handling for the double-operand block move.
string opstr1 = PseudoOp.FormatNumericOperand(formatter, proj.SymbolTable,
gen.Localizer.LabelMap, dfd, operand >> 8, 1,
PseudoOp.FormatNumericOpFlags.OmitLabelPrefixSuffix);
string opstr2 = PseudoOp.FormatNumericOperand(formatter, proj.SymbolTable,
gen.Localizer.LabelMap, dfd, operand & 0xff, 1,
PseudoOp.FormatNumericOpFlags.OmitLabelPrefixSuffix);
if (gen.Quirks.BlockMoveArgsReversed)
{
string tmp = opstr1;
opstr1 = opstr2;
opstr2 = tmp;
}
string hash = gen.Quirks.BlockMoveArgsNoHash ? "" : "#";
formattedOperand = hash + opstr1 + "," + hash + opstr2;
}
else
{
if (attr.DataDescriptor.IsStringOrCharacter)
{
gen.UpdateCharacterEncoding(dfd);
}
formattedOperand = PseudoOp.FormatNumericOperand(formatter, proj.SymbolTable,
lvLookup, gen.Localizer.LabelMap, dfd,
offset, operandForSymbol, operandLen, opFlags);
}
}
else
{
// Show operand value in hex.
if (op.AddrMode == OpDef.AddressMode.BlockMove)
{
int arg1, arg2;
if (gen.Quirks.BlockMoveArgsReversed)
{
arg1 = operand & 0xff;
arg2 = operand >> 8;
}
else
{
arg1 = operand >> 8;
arg2 = operand & 0xff;
}
string hash = gen.Quirks.BlockMoveArgsNoHash ? "" : "#";
formattedOperand = hash + formatter.FormatHexValue(arg1, 2) + "," +
hash + formatter.FormatHexValue(arg2, 2);
}
else
{
if (operandLen == 2)
{
// This is necessary for 16-bit operands, like "LDA abs" and "PEA val",
// when outside bank zero. The bank is included in the operand address,
// but we don't want to show it here.
operandForSymbol &= 0xffff;
}
formattedOperand = formatter.FormatHexValue(operandForSymbol, operandLen * 2);
}
}
string operandStr = formatter.FormatOperand(op, formattedOperand, wdis);
if (gen.Quirks.StackIntOperandIsImmediate && op.AddrMode == OpDef.AddressMode.StackInt)
{
// COP $02 is standard, but some require COP #$02
operandStr = '#' + operandStr;
}
string eolComment = proj.Comments[offset];
if (doAddCycles)
{
bool branchCross = (attr.Address & 0xff00) != (operandForSymbol & 0xff00);
int cycles = proj.CpuDef.GetCycles(op.Opcode, attr.StatusFlags, attr.BranchTaken,
branchCross);
if (cycles > 0)
{
if (!string.IsNullOrEmpty(eolComment))
{
eolComment = cycles.ToString() + " " + eolComment;
}
else
{
eolComment = cycles.ToString();
}
}
else
{
if (!string.IsNullOrEmpty(eolComment))
{
eolComment = (-cycles).ToString() + "+ " + eolComment;
}
else
{
eolComment = (-cycles).ToString() + "+";
}
}
}
string commentStr = formatter.FormatEolComment(eolComment);
string replMnemonic = gen.ModifyOpcode(offset, op);
if (attr.Length != instrBytes)
{
// This instruction has another instruction inside it. Throw out what we
// computed and just output as bytes.
gen.GenerateShortSequence(offset, instrBytes, out opcodeStr, out operandStr);
}
else if (isPcRelBankWrap && gen.Quirks.NoPcRelBankWrap)
{
// Some assemblers have trouble generating PC-relative operands that wrap
// around the bank. Output as raw hex.
gen.GenerateShortSequence(offset, instrBytes, out opcodeStr, out operandStr);
}
else if (op.AddrMode == OpDef.AddressMode.BlockMove &&
gen.Quirks.BlockMoveArgsReversed)
{
// On second thought, just don't even output the wrong thing.
gen.GenerateShortSequence(offset, instrBytes, out opcodeStr, out operandStr);
}
else if (replMnemonic == null)
{
// No mnemonic exists for this opcode.
gen.GenerateShortSequence(offset, instrBytes, out opcodeStr, out operandStr);
}
else if (replMnemonic != string.Empty)
{
// A replacement mnemonic has been provided.
opcodeStr = formatter.FormatMnemonic(replMnemonic, wdis);
}
gen.OutputLine(labelStr, opcodeStr, operandStr, commentStr);
// Assemblers like Merlin32 try to be helpful and track SEP/REP, but they do the
// wrong thing if we're in emulation mode. Force flags back to short.
if (proj.CpuDef.HasEmuFlag && gen.Quirks.TracksSepRepNotEmu && op == OpDef.OpREP_Imm)
{
if ((operand & 0x30) != 0 && attr.StatusFlags.E == 1)
{
gen.OutputRegWidthDirective(offset, 0, 0, 1, 1);
}
}
}
private static void GenerateInstruction(IGenerator gen, StreamWriter sw,
LocalVariableLookup lvLookup, int offset, int instrBytes, bool doAddCycles)
{
DisasmProject proj = gen.Project;
Formatter formatter = gen.SourceFormatter;
byte[] data = proj.FileData;
Anattrib attr = proj.GetAnattrib(offset);
string labelStr = string.Empty;
if (attr.Symbol != null)
{
labelStr = gen.Localizer.ConvLabel(attr.Symbol.Label);
}
OpDef op = proj.CpuDef.GetOpDef(data[offset]);
int operand = op.GetOperand(data, offset, attr.StatusFlags);
int instrLen = op.GetLength(attr.StatusFlags);
OpDef.WidthDisambiguation wdis = OpDef.WidthDisambiguation.None;
if (op.IsWidthPotentiallyAmbiguous)
{
wdis = OpDef.GetWidthDisambiguation(instrLen, operand);
}
if (gen.Quirks.SinglePassAssembler && wdis == OpDef.WidthDisambiguation.None &&
(op.AddrMode == OpDef.AddressMode.DP ||
op.AddrMode == OpDef.AddressMode.DPIndexX) ||
op.AddrMode == OpDef.AddressMode.DPIndexY)
{
// Could be a forward reference to a direct-page label. For ACME, we don't
// care if it's forward or not.
if ((gen.Quirks.SinglePassNoLabelCorrection && IsLabelReference(gen, offset)) ||
IsForwardLabelReference(gen, offset))
{
wdis = OpDef.WidthDisambiguation.ForceDirect;
}
}
if (wdis == OpDef.WidthDisambiguation.ForceLongMaybe &&
gen.Quirks.SinglePassAssembler &&
IsForwardLabelReference(gen, offset))
{
// Assemblers like cc65 can't tell if a symbol reference is Absolute or
// Long if they haven't seen the symbol yet. Irrelevant for ACME, which
// doesn't currently handle 65816 outside bank 0.
wdis = OpDef.WidthDisambiguation.ForceLong;
}
string opcodeStr = formatter.FormatOpcode(op, wdis);
string formattedOperand = null;
int operandLen = instrLen - 1;
PseudoOp.FormatNumericOpFlags opFlags =
PseudoOp.FormatNumericOpFlags.OmitLabelPrefixSuffix;
bool isPcRelBankWrap = false;
// Tweak branch instructions. We want to show the absolute address rather
// than the relative offset (which happens with the OperandAddress assignment
// below), and 1-byte branches should always appear as a 4-byte hex value.
// Unless we're outside bank 0 on 65816, in which case most assemblers require
// them to be 6-byte hex values.
if (op.AddrMode == OpDef.AddressMode.PCRel ||
op.AddrMode == OpDef.AddressMode.DPPCRel)
{
Debug.Assert(attr.OperandAddress >= 0);
operandLen = 2;
opFlags |= PseudoOp.FormatNumericOpFlags.IsPcRel;
}
else if (op.AddrMode == OpDef.AddressMode.PCRelLong ||
op.AddrMode == OpDef.AddressMode.StackPCRelLong)
{
opFlags |= PseudoOp.FormatNumericOpFlags.IsPcRel;
}
else if (op.AddrMode == OpDef.AddressMode.Imm ||
op.AddrMode == OpDef.AddressMode.ImmLongA ||
op.AddrMode == OpDef.AddressMode.ImmLongXY)
{
opFlags |= PseudoOp.FormatNumericOpFlags.HasHashPrefix;
}
if ((opFlags & PseudoOp.FormatNumericOpFlags.IsPcRel) != 0)
{
int branchDist = attr.Address - attr.OperandAddress;
isPcRelBankWrap = branchDist > 32767 || branchDist < -32768;
}
if (op.IsAbsolutePBR)
{
opFlags |= PseudoOp.FormatNumericOpFlags.IsAbsolutePBR;
}
if (gen.Quirks.BankZeroAbsPBRRestrict)
{
// Hack to avoid having to define a new FormatConfig.ExpressionMode for 64tass.
// Get rid of this 64tass gets its own exp mode.
opFlags |= PseudoOp.FormatNumericOpFlags.Is64Tass;
}
// 16-bit operands outside bank 0 need to include the bank when computing
// symbol adjustment.
int operandForSymbol = operand;
if (attr.OperandAddress >= 0)
{
operandForSymbol = attr.OperandAddress;
}
// Check Length to watch for bogus descriptors. (ApplyFormatDescriptors() should
// now be screening bad descriptors out, so we may not need the Length test.)
if (attr.DataDescriptor != null && attr.Length == attr.DataDescriptor.Length)
{
FormatDescriptor dfd = gen.ModifyInstructionOperandFormat(offset,
attr.DataDescriptor, operand);
// Format operand as directed.
if (op.AddrMode == OpDef.AddressMode.BlockMove)
{
// Special handling for the double-operand block move.
string opstr1 = PseudoOp.FormatNumericOperand(formatter, proj.SymbolTable,
gen.Localizer.LabelMap, dfd, operand >> 8, 1,
PseudoOp.FormatNumericOpFlags.OmitLabelPrefixSuffix);
string opstr2 = PseudoOp.FormatNumericOperand(formatter, proj.SymbolTable,
gen.Localizer.LabelMap, dfd, operand & 0xff, 1,
PseudoOp.FormatNumericOpFlags.OmitLabelPrefixSuffix);
if (gen.Quirks.BlockMoveArgsReversed)
{
string tmp = opstr1;
opstr1 = opstr2;
opstr2 = tmp;
}
string hash = gen.Quirks.BlockMoveArgsNoHash ? "" : "#";
formattedOperand = hash + opstr1 + "," + hash + opstr2;
}
else if (op.AddrMode == OpDef.AddressMode.DPPCRel)
{
// Special handling for double-operand BBR/BBS. The instruction generally
// behaves like a branch, so format that first.
string branchStr = PseudoOp.FormatNumericOperand(formatter,
proj.SymbolTable, gen.Localizer.LabelMap, dfd,
operandForSymbol, operandLen, opFlags);
string dpStr = formatter.FormatHexValue(operand & 0xff, 2);
formattedOperand = dpStr + "," + branchStr;
}
else
{
if (attr.DataDescriptor.IsStringOrCharacter)
{
gen.UpdateCharacterEncoding(dfd);
}
formattedOperand = PseudoOp.FormatNumericOperand(formatter, proj.SymbolTable,
lvLookup, gen.Localizer.LabelMap, dfd,
offset, operandForSymbol, operandLen, opFlags);
}
}
else
{
// Show operand value in hex.
if (op.AddrMode == OpDef.AddressMode.BlockMove)
{
int arg1, arg2;
if (gen.Quirks.BlockMoveArgsReversed)
{
arg1 = operand & 0xff;
arg2 = operand >> 8;
}
else
{
arg1 = operand >> 8;
arg2 = operand & 0xff;
}
string hash = gen.Quirks.BlockMoveArgsNoHash ? "" : "#";
formattedOperand = hash + formatter.FormatHexValue(arg1, 2) + "," +
hash + formatter.FormatHexValue(arg2, 2);
}
else if (op.AddrMode == OpDef.AddressMode.DPPCRel)
{
formattedOperand = formatter.FormatHexValue(operand & 0xff, 2) + "," +
formatter.FormatHexValue(operandForSymbol, operandLen * 2);
}
else
{
if (operandLen == 2 && !(op.IsAbsolutePBR && gen.Quirks.Need24BitsForAbsPBR) &&
(opFlags & PseudoOp.FormatNumericOpFlags.IsPcRel) == 0)
{
// This is necessary for 16-bit operands, like "LDA abs" and "PEA val",
// when outside bank zero. The bank is included in the operand address,
// but we don't want to show it here. We may need it for JSR/JMP though,
// and the bank is required for relative branch instructions.
operandForSymbol &= 0xffff;
}
formattedOperand = formatter.FormatHexValue(operandForSymbol, operandLen * 2);
}
}
string operandStr = formatter.FormatOperand(op, formattedOperand, wdis);
if (gen.Quirks.StackIntOperandIsImmediate &&
op.AddrMode == OpDef.AddressMode.StackInt)
{
// COP $02 is standard, but some require COP #$02
operandStr = '#' + operandStr;
}
// The BBR/BBS/RMB/SMB instructions include a bit index (0-7). The standard way is
// to make it part of the mnemonic, but some assemblers make it an argument.
if (gen.Quirks.BitNumberIsArg && op.IsNumberedBitOp)
{
// Easy way: do some string manipulation.
char bitIndex = opcodeStr[opcodeStr.Length - 1];
opcodeStr = opcodeStr.Substring(0, opcodeStr.Length - 1);
operandStr = bitIndex.ToString() + "," + operandStr;
}
string eolComment = proj.Comments[offset];
if (doAddCycles)
{
bool branchCross = (attr.Address & 0xff00) != (operandForSymbol & 0xff00);
int cycles = proj.CpuDef.GetCycles(op.Opcode, attr.StatusFlags, attr.BranchTaken,
branchCross);
if (cycles > 0)
{
if (!string.IsNullOrEmpty(eolComment))
{
eolComment = cycles.ToString() + " " + eolComment;
}
else
{
eolComment = cycles.ToString();
}
}
else
{
if (!string.IsNullOrEmpty(eolComment))
{
eolComment = (-cycles).ToString() + "+ " + eolComment;
}
else
{
eolComment = (-cycles).ToString() + "+";
}
}
}
string commentStr = formatter.FormatEolComment(eolComment);
string replMnemonic = gen.ModifyOpcode(offset, op);
if (attr.Length != instrBytes)
{
// This instruction has another instruction inside it. Throw out what we
// computed and just output as bytes.
// TODO: in some odd situations we can split something that doesn't need
// to be split (see note at end of #107). Working around the problem at
// this stage is a little awkward because I think we need to check for the
// presence of labels on one or more later lines.
gen.GenerateShortSequence(offset, instrBytes, out opcodeStr, out operandStr);
}
else if (isPcRelBankWrap && gen.Quirks.NoPcRelBankWrap)
{
// Some assemblers have trouble generating PC-relative operands that wrap
// around the bank. Output as raw hex.
gen.GenerateShortSequence(offset, instrBytes, out opcodeStr, out operandStr);
}
else if (op.AddrMode == OpDef.AddressMode.BlockMove &&
gen.Quirks.BlockMoveArgsReversed)
{
// On second thought, just don't even output the wrong thing.
gen.GenerateShortSequence(offset, instrBytes, out opcodeStr, out operandStr);
}
else if (replMnemonic == null)
{
// No mnemonic exists for this opcode.
gen.GenerateShortSequence(offset, instrBytes, out opcodeStr, out operandStr);
}
else if (replMnemonic != string.Empty)
{
// A replacement mnemonic has been provided.
opcodeStr = formatter.FormatMnemonic(replMnemonic, wdis);
}
gen.OutputLine(labelStr, opcodeStr, operandStr, commentStr);
// Assemblers like Merlin32 try to be helpful and track SEP/REP, but they do the
// wrong thing if we're in emulation mode. Force flags back to short.
if (proj.CpuDef.HasEmuFlag && gen.Quirks.TracksSepRepNotEmu && op == OpDef.OpREP_Imm)
{
if ((operand & 0x30) != 0 && attr.StatusFlags.IsEmulationMode)
{
gen.OutputRegWidthDirective(offset, 0, 0, 1, 1);
}
}
}
