public VHDLInstantiation(VHDLFile container, LibElemInst instantiation, LibraryElement libElement, Command callee)
{
m_container = container;
m_instantation = instantiation;
m_libraryElement = libElement;
IntergrateIntoContainer(callee);
}
protected override void DoCommandAction()
{
Stream stream = null;
LibraryElement libElement = Objects.Library.Instance.GetElement(LibraryElementName);
try
{
stream = File.Open(FileName, FileMode.Create);
BinaryFormatter formatter = new BinaryFormatter();
formatter.Serialize(stream, libElement);
}
catch (Exception error)
{
throw new ArgumentException("Could not serialize library element: " + error.Message);
}
finally
{
stream.Close();
}
// update the restore command for the library element
AddBinaryLibraryElement addElCmd = new AddBinaryLibraryElement();
addElCmd.FileName = FileName;
libElement.LoadCommand = addElCmd.ToString();
}
private LibraryElement GetLibraryElement()
{
LibraryElement el = new LibraryElement();
el.Name = Name;
el.PrimitiveName = BELType;
el.VHDLGenericMap = "generic map ( INIT => X\"ABCDABCDABCDABCD\" )";
el.Containter = new XDLModule();
el.VivadoConnectionPrimitive = true;
// add outpin
XDLPort outPort = new XDLPort();
outPort.Direction = FPGATypes.PortDirection.Out;
outPort.ExternalName = "O";
outPort.InstanceName = "unknown";
outPort.SlicePort = "unknown";
el.Containter.Add(outPort);
// add inpins
for (int i = 0; i < LUT_SIZE; i++)
{
AddXDLPort(el, $"I{i}", FPGATypes.PortDirection.In);
}
return(el);
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
LibElemInst inst = LibraryElementInstanceManager.Instance.GetInstantiation(InstanceName);
LibraryElement libElement = Objects.Library.Instance.GetElement(inst.LibraryElementName);
Tile anchorCLB = FPGA.FPGA.Instance.GetTile(inst.AnchorLocation);
NetlistContainer netlistContainer = GetNetlistContainer();
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
RelocateInstancesForXDL(libElement, anchorCLB, (XDLContainer)netlistContainer);
RelocateNetsForXDL(libElement, anchorCLB, (XDLContainer)netlistContainer);
// add design config
if (AddDesignConfig && libElement.Containter is XDLContainer && ((XDLContainer)netlistContainer).GetDesignConfig().Length == 0)
{
((XDLContainer)netlistContainer).AddDesignConfig(((XDLContainer)libElement.Containter).GetDesignConfig());
}
break;
case FPGATypes.BackendType.Vivado:
RelocateInstancesForTCL(libElement, anchorCLB, (TCLContainer)netlistContainer);
RelocateNetsForTCL(libElement, anchorCLB, netlistContainer);
break;
}
}
/// <summary>
/// copy and relocate the net
/// </summary>
/// <param name="other"></param>
public static TCLNet Relocate(TCLNet other,LibraryElement libElement,Tile anchor)
{
TCLNet copiedNet = new TCLNet(other.Name);
copiedNet.RoutingTree = new TCLRoutingTree(other.RoutingTree);
foreach (TCLRoutingTreeNode node in copiedNet.RoutingTree.GetAllRoutingNodes().Where(n => n.Tile != null))
{
string targetLocation = "";
bool success = libElement.GetTargetLocation(node.Tile.Location, anchor, out targetLocation);
Tile targetTile = FPGA.FPGA.Instance.GetTile(targetLocation);
node.Tile = targetTile;
}
copiedNet.m_footerComment.Append(other.FooterComment);
copiedNet.Properties = new TCLProperties(other.Properties);
copiedNet.m_netPins = new List <NetPin>();
foreach (NetPin pin in other.NetPins)
{
NetPin copiedPin = NetPin.Copy(pin);
copiedNet.m_netPins.Add(copiedPin);
string targetLocation = "";
bool success = libElement.GetTargetLocation(pin.TileName, anchor, out targetLocation);
Tile targetTile = FPGA.FPGA.Instance.GetTile(targetLocation);
pin.TileName = targetTile.Location;
}
copiedNet.IsBlockerNet = other.IsBlockerNet;
copiedNet.NodeNet = other.NodeNet;
if (other.OutpinInstance != null)
{
copiedNet.OutpinInstance = new TCLInstance((TCLInstance)other.OutpinInstance);
}
return(copiedNet);
}
private void m_btnPlaceInSelection_Click(object sender, EventArgs e)
{
string macroName = null;
string errorMessage = null;
string instanceName = null;
string netlistContainerName = null;
bool paramsValid = FindParametersForMultiInstantiation(out macroName, out instanceName, out netlistContainerName, out errorMessage);
if (!paramsValid)
{
MessageBox.Show(errorMessage, "Error", MessageBoxButtons.OK);
return;
}
LibraryElement el = Library.Instance.GetElement(macroName);
AddInstantiationInSelectedTiles cmd = new AddInstantiationInSelectedTiles();
cmd.AutoClearModuleSlot = m_chkBoxAutoclearMulti.Checked;
cmd.Horizontal = m_drpDownHorizontalOrder.Text;
cmd.InstanceName = instanceName;
cmd.LibraryElementName = macroName;
cmd.Mode = m_drpDownMode.Text;
cmd.NetlistContainerName = netlistContainerName;
cmd.SliceNumber = el.ResourceShape.Anchor.AnchorSliceNumber;
cmd.Vertical = m_drpDownVerticallOrder.Text;
Commands.CommandExecuter.Instance.Execute(cmd);
}
private bool IsPlacementValidForMultiInstantiation()
{
string libElementName = null;
string errorMessage = null;
string instanceName = null;
string netlistContainerName = null;
bool paramsValid = FindParametersForMultiInstantiation(out libElementName, out instanceName, out netlistContainerName, out errorMessage);
if (!paramsValid)
{
MessageBox.Show(errorMessage, "Error", MessageBoxButtons.OK, MessageBoxIcon.Error);
return(false);
}
foreach (Tile clb in TileSelectionManager.Instance.GetSelectedTiles().Where(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB)))
{
StringBuilder errorList = null;
LibraryElement libElement = Library.Instance.GetElement(libElementName);
bool placementOk = DesignRuleChecker.CheckLibraryElementPlacement(clb, libElement, out errorList);
if (!placementOk)
{
MessageBox.Show("Library element " + libElementName + " can not be placed at " + clb.Location + ": " + errorList.ToString(), "Placement failed", MessageBoxButtons.OK, MessageBoxIcon.Error);
return(false);
}
}
// placement is ok
int clbsInSelection = TileSelectionManager.Instance.GetSelectedTiles().Count(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
MessageBox.Show("Library element " + libElementName + " can be placed at the selected " + clbsInSelection + " position(s)", "Placement OK", MessageBoxButtons.OK, MessageBoxIcon.Asterisk);
return(true);
}
protected override void DoCommandAction()
{
CheckParameters();
LibraryElement libraryElement = GetLibraryElement();
Objects.Library.Instance.Add(libraryElement);
}
protected override void DoCommandAction()
{
LibraryElement libElement = Objects.Library.Instance.GetElement(LibraryElementName);
Tile anchor = FPGA.FPGA.Instance.GetTile(AnchorLocation);
if (libElement.ResourceShape.Anchor.AnchorSliceNumber >= anchor.Slices.Count)
{
throw new ArgumentException("Too few slices on tile " + anchor.Location + ". Expecting " + libElement.ResourceShape.Anchor.AnchorSliceNumber + " but found " + anchor.Slices.Count + " slice.");
}
if (IdentifierManager.Instance.IsMatch(anchor.Location, IdentifierManager.RegexTypes.Interconnect))
{
anchor = FPGATypes.GetCLTile(anchor).FirstOrDefault();
}
if (AutoClearModuleSlot)
{
//this.FastAutoClearModuleSlotBeforeInstantiation(libElement, Enumerable.Repeat(anchor, 1));
AutoClearModuleSlotBeforeInstantiation(libElement, Enumerable.Repeat(anchor, 1));
}
LibElemInst instantiation = new LibElemInst();
instantiation.AnchorLocation = AnchorLocation;
instantiation.InstanceName = Hierarchy + InstanceName;
instantiation.LibraryElementName = LibraryElementName;
instantiation.SliceNumber = libElement.ResourceShape.Anchor.AnchorSliceNumber;
instantiation.SliceName = anchor.Slices[(int)libElement.ResourceShape.Anchor.AnchorSliceNumber].SliceName;
LibraryElementInstanceManager.Instance.Add(instantiation);
// mark source as blocked
ExcludeInstantiationSourcesFromBlocking markSrc = new ExcludeInstantiationSourcesFromBlocking();
markSrc.AnchorLocation = AnchorLocation;
markSrc.LibraryElementName = LibraryElementName;
CommandExecuter.Instance.Execute(markSrc);
SaveLibraryElementInstantiation saveCmd = new SaveLibraryElementInstantiation();
saveCmd.AddDesignConfig = false;
saveCmd.InsertPrefix = true;
saveCmd.InstanceName = InstanceName;
saveCmd.NetlistContainerName = NetlistContainerName;
CommandExecuter.Instance.Execute(saveCmd);
if (AutoFuse)
{
FuseNets fuseCmd = new FuseNets();
fuseCmd.NetlistContainerName = NetlistContainerName;
fuseCmd.Mute = Mute;
fuseCmd.Profile = Profile;
fuseCmd.PrintProgress = PrintProgress;
CommandExecuter.Instance.Execute(fuseCmd);
}
}
private void AddXDLPort(LibraryElement el, string prefix, int index, FPGATypes.PortDirection dir, bool makeInputsConstant)
{
XDLPort p = new XDLPort();
p.Direction = dir;
p.ExternalName = prefix + index;
p.InstanceName = "unknown";
p.SlicePort = "unknown";
p.ConstantValuePort = makeInputsConstant;
el.Containter.Add(p);
}
private void AddXDLPort(LibraryElement el, string portName, FPGATypes.PortDirection dir)
{
XDLPort p = new XDLPort();
p.Direction = dir;
p.ExternalName = portName;
p.InstanceName = "unknown";
p.SlicePort = "unknown";
p.ConstantValuePort = false;
el.Containter.Add(p);
}
protected override void DoCommandAction()
{
if (!Objects.Library.Instance.Contains(LibraryElementName))
{
throw new ArgumentException("A library element named " + LibraryElementName + " was not found");
}
if (TileSelectionManager.Instance.NumberOfSelectedTiles == 0)
{
throw new ArgumentException("No tiles are selected, can not derive module shape");
}
LibraryElement libElement = Objects.Library.Instance.GetElement(LibraryElementName);
// enrich library element with selection command for auto clear
libElement.ResourceShape = new Shape();
foreach (Tile t in TileSelectionManager.Instance.GetSelectedTiles())
{
libElement.ResourceShape.Add(t.Location);
}
List <Tile> possibleAnchors = new List <Tile>();
foreach (IdentifierManager.RegexTypes anchorType in new IdentifierManager.RegexTypes[] { IdentifierManager.RegexTypes.CLB, IdentifierManager.RegexTypes.DSP, IdentifierManager.RegexTypes.BRAM })
{
Tile upperLeftTile = TileSelectionManager.Instance.GetSelectedTile(IdentifierManager.Instance.GetRegex(anchorType), FPGATypes.Placement.UpperLeft);
if (upperLeftTile != null)
{
possibleAnchors.Add(upperLeftTile);
}
}
if (possibleAnchors.Count == 0)
{
throw new ArgumentException("No upper left tile of either type CLB, DSP or BRAM found. Can not derive any anchor.");
}
Tile anchor = possibleAnchors.OrderBy(t => t.TileKey.X).First();
libElement.ResourceShape.Anchor.AnchorTileLocation = anchor.Location;
libElement.ResourceShape.Anchor.AnchorLocationX = anchor.LocationX;
libElement.ResourceShape.Anchor.AnchorLocationY = anchor.LocationY;
libElement.ResourceShape.Anchor.AnchorSliceNumber = 0;
libElement.ResourceShape.Anchor.AnchorSliceName = anchor.Slices[0].SliceName;
/*
* Tile upperLeftCLB = TileSelectionManager.Instance.GetSelectedTile(IdentifierManager.Instance.GetRegex(IdentifierManager.RegexTypes.CLBRegex), FPGATypes.Placement.UpperLeft);
* libElement.ResourceShape.AnchorTileLocation = upperLeftCLB.Location;
* libElement.ResourceShape.AnchorLocationX = upperLeftCLB.LocationX;
* libElement.ResourceShape.AnchorLocationY = upperLeftCLB.LocationY;
* libElement.ResourceShape.AnchorSliceNumber = 0;
* libElement.ResourceShape.AnchorSliceName = upperLeftCLB.Slices[0].SliceName;*/
}
private IEnumerable <XElement> GetSerializedProperies(LibraryElement libraryElement)
{
if (!ValidatePropertiesWithCallBack(libraryElement))
{
return(null);
}
return(libraryElement
.GetType()
.GetProperties()
.Select(property => new XElement(property.Name, property.GetValue(libraryElement))));
}
private LibraryElement GetFF(string belName, bool makeInputsConstant, string inputPortPrefix, string outputPort)
{
LibraryElement el = new LibraryElement();
el.SliceNumber = SliceNumber;
el.Name = belName;
el.PrimitiveName = BELType;
el.BEL = belName;
el.LoadCommand = ToString();
el.Containter = new NetlistContainer();
el.VHDLGenericMap = "generic map ( INIT => '0' )";
el.Containter = new XDLModule();
el.VivadoConnectionPrimitive = true;
// Q output
XDLPort q = new XDLPort();
q.Direction = FPGATypes.PortDirection.Out;
q.ExternalName = "Q";
q.InstanceName = "unknown";
q.SlicePort = "unknown";
el.Containter.Add(q);
List <string> inputs = new List <string>();
inputs.Add("D");
inputs.Add("C");
inputs.Add("CE");
inputs.Add("R");
foreach (string i in inputs)
{
XDLPort p = new XDLPort();
p.Direction = FPGATypes.PortDirection.In;
p.ExternalName = i;
p.InstanceName = "unknown";
p.SlicePort = "unknown";
p.ConstantValuePort = false;
el.Containter.Add(p);
}
;
Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
foreach (string stopOverPortName in StopOverPorts)
{
el.AddPortToBlock(interconnect, new Port(stopOverPortName));
}
return(el);
}
protected override void DoCommandAction()
{
NetlistContainer netlistContainer = GetNetlistContainer();
Slice anchor = FPGA.FPGA.Instance.GetSlice(SliceName);
LibraryElement libElement = Objects.Library.Instance.GetElement(LibraryElementName);
if (anchor == null)
{
throw new ArgumentException("Can not find Slice " + SliceName);
}
if (AutoClearModuleSlot)
{
AutoClearModuleSlotBeforeInstantiation(libElement, Enumerable.Repeat(anchor.ContainingTile, 1));
}
LibElemInst instantiation = new LibElemInst();
instantiation.AnchorLocation = anchor.ContainingTile.Location;
instantiation.InstanceName = Hierarchy + InstanceName;
instantiation.LibraryElementName = LibraryElementName;
instantiation.SliceNumber = anchor.ContainingTile.GetSliceNumberByName(SliceName);
instantiation.SliceName = SliceName;
LibraryElementInstanceManager.Instance.Add(instantiation);
// mark source as blocked
ExcludeInstantiationSourcesFromBlocking markSrc = new ExcludeInstantiationSourcesFromBlocking();
markSrc.AnchorLocation = anchor.ContainingTile.Location;
markSrc.LibraryElementName = LibraryElementName;
CommandExecuter.Instance.Execute(markSrc);
SaveLibraryElementInstantiation saveCmd = new SaveLibraryElementInstantiation();
saveCmd.AddDesignConfig = false;
saveCmd.InsertPrefix = true;
saveCmd.InstanceName = InstanceName;
saveCmd.NetlistContainerName = NetlistContainerName;
CommandExecuter.Instance.Execute(saveCmd);
if (AutoFuse)
{
FuseNets fuseCmd = new FuseNets();
fuseCmd.NetlistContainerName = NetlistContainerName;
fuseCmd.Mute = Mute;
fuseCmd.Profile = Profile;
fuseCmd.PrintProgress = PrintProgress;
CommandExecuter.Instance.Execute(fuseCmd);
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
// read file
DesignParser parser = DesignParser.CreateDesignParser(FileName);
XDLContainer container = new XDLContainer();
// into design
parser.ParseDesign(container, this);
// derive name from file
string elementName = Path.GetFileNameWithoutExtension(FileName);
if (container.ModuleCount != 0)
{
// find ports to block and assign them to slices
// as we want to either
// connect these ports (if used) or
// drive a '1' to (if unused)
foreach (XDLModule module in container.Modules)
{
// new library element to be added to library
LibraryElement libElement = new LibraryElement();
libElement.Containter = module;
libElement.Name = elementName;
libElement.PrimitiveName = elementName;
libElement.LoadCommand = ToString();
// add lib element to library, BEFORE deriving block data as command SaveXDLLibraryElementAsBinaryLibraryElement access the element in the library
Objects.Library.Instance.Add(libElement);
DeriveBlockingData(libElement);
}
}
else
{
// new library element to be added to library
LibraryElement libElement = new LibraryElement();
libElement.Containter = container;
libElement.Name = elementName;
libElement.PrimitiveName = elementName;
libElement.LoadCommand = ToString();
// add lib element to library, BEFORE deriving block data as command SaveXDLLibraryElementAsBinaryLibraryElement access the element in the library
Objects.Library.Instance.Add(libElement);
DeriveBlockingData(libElement);
}
}
protected override void DoCommandAction()
{
CheckParameter();
LibraryElement main;
if (Objects.Library.Instance.Contains(Name))
{
main = Objects.Library.Instance.GetElement(Name);
}
else
{
main = new LibraryElement();
main.Name = Name;
main.VivadoConnectionPrimitive = true;
main.Containter = new NetlistContainer();
Objects.Library.Instance.Add(main);
}
for (int i = 0; i < BELs.Count; i++)
{
string bel = BELs[i];
string prefix = InputBELinputPortPrefix[i];
string outputPort = BELOutputPorts[i];
string initValue = InitValues[i];
LibraryElement elem = GetLibraryElement(bel, false, prefix, outputPort, initValue);
main.Add(elem);
Objects.Library.Instance.Add(elem);
}
/*
* LibElem a = this.GetLUT6LibraryElement("A", true);
* LibElem b = this.GetLUT6LibraryElement("B", true);
* LibElem c = this.GetLUT6LibraryElement("C", false);
* LibElem d = this.GetLUT6LibraryElement("D", true);
*
* main.Add(a);
* main.Add(b);
* main.Add(c);
* main.Add(d);
*
* Objects.Library.Instance.Add(main);
* Objects.Library.Instance.Add(a);
* Objects.Library.Instance.Add(b);
* Objects.Library.Instance.Add(c);
* Objects.Library.Instance.Add(d);
* */
}
private LibraryElement GetLUT(string belName, bool makeInputsConstant, string inputPortPrefix, string outputPort, string initValue)
{
int lutSize = 6;
LibraryElement el = new LibraryElement();
el.SliceNumber = SliceNumber;
el.Name = belName;
el.PrimitiveName = BELType;
el.BEL = belName;
el.LoadCommand = ToString();
el.Containter = new NetlistContainer();
el.VHDLGenericMap = "generic map ( INIT => X\"" + initValue + "\" )";
el.Containter = new XDLModule();
el.VivadoConnectionPrimitive = true;
// one output per LUT
XDLPort outPort = new XDLPort();
outPort.Direction = FPGATypes.PortDirection.Out;
outPort.ExternalName = "O";
outPort.InstanceName = "unknown";
outPort.SlicePort = "unknown";
el.Containter.Add(outPort);
// six inputs I=..I5
for (int i = 0; i < lutSize; i++)
{
AddXDLPort(el, "I", i, FPGATypes.PortDirection.In, makeInputsConstant);
}
Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
List <string> lutPortNames = new List <string>();
// see LUTRouting tab
for (int i = 1; i <= lutSize; i++)
{
lutPortNames.Add(inputPortPrefix + i);
}
foreach (string stopOverPortName in StopOverPorts)
{
el.AddPortToBlock(interconnect, new Port(stopOverPortName));
}
return(el);
}
protected override void DoCommandAction()
{
CheckParameters();
LibraryElement mainElement = GetMainElement();
for (int i = 0; i < BELs.Count; i++)
{
string bel = BELs[i];
string prefix = InputBELinputPortPrefix[i];
string outputPort = BELOutputPorts[i];
LibraryElement elem = GetOtherElement(bel, !bel.Equals(InputBEL), prefix, outputPort);
mainElement.Add(elem);
Objects.Library.Instance.Add(elem);
}
}
private LibraryElement GetMainElement()
{
if (Objects.Library.Instance.Contains(Name))
{
return(Objects.Library.Instance.GetElement(Name));
}
LibraryElement newElement = new LibraryElement
{
Name = Name,
VivadoConnectionPrimitive = true,
Containter = new NetlistContainer()
};
Objects.Library.Instance.Add(newElement);
return(newElement);
}
private void TraverseBackwards(LibraryElement element, Tile clb, Tile interconnect, BELInfo info)
{
List <string> lutPortNames = new List <string>();
// see LUTRouting tab
for (int i = 1; i <= info.type.inputNames.Count; i++)
{
lutPortNames.Add(info.inputPortPrefix + i);
}
foreach (string s in lutPortNames)
{
// travers backwards into INT
foreach (Tuple <Port, Port> t in clb.SwitchMatrix.GetAllArcs().Where(a => a.Item2.Name.EndsWith(s)))
{
element.AddPortToBlock(clb, t.Item1);
element.AddPortToBlock(clb, t.Item2);
if (interconnect.WireList == null)
{
OutputManager.WriteWarning("No wire list found on " + interconnect.Location);
}
else
{
foreach (Wire w in interconnect.WireList.Where(w => w.PipOnOtherTile.Equals(t.Item1.Name)))
{
element.AddPortToBlock(interconnect, new FPGA.Port(w.LocalPip));
}
}
}
}
// we always need to exclude the port from the LUT output from blocking
// assuming name
foreach (Tuple <Port, Port> t in clb.SwitchMatrix.GetAllArcs().Where(a => a.Item1.Name.EndsWith(info.outputPort)))
{
// no realy neccessary
element.AddPortToBlock(clb, t.Item1);
element.AddPortToBlock(clb, t.Item2);
foreach (Wire w in clb.WireList.Where(w => w.LocalPip.Equals(t.Item2.Name)))
{
element.AddPortToBlock(interconnect, new Port(w.PipOnOtherTile));
}
}
}
private void RelocateNetsForTCL(LibraryElement libElement, Tile anchorCLB, NetlistContainer netlistContainer)
{
foreach (TCLNet net in libElement.Containter.Nets)
{
TCLNet relocatedNet = TCLNet.Relocate(net, libElement, anchorCLB);
relocatedNet.Name = InstanceName + relocatedNet.Name;
// relocate NetPins
foreach (NetPin pin in relocatedNet.NetPins)
{
if (InsertPrefix)
{
pin.InstanceName = InstanceName + pin.InstanceName;
}
}
netlistContainer.Add(relocatedNet);
}
}
private LibraryElement GetBEL(BELInfo info)
{
LibraryElement element = new LibraryElement
{
SliceNumber = SliceNumber,
Name = info.belName,
PrimitiveName = BELType,
BEL = info.belName,
LoadCommand = ToString(),
Containter = new XDLModule(),
VHDLGenericMap = info.type.VHDLGenericMap,
VivadoConnectionPrimitive = true
};
// Outputs
foreach (string output in info.type.outputNames)
{
element.Containter.Add(MakeXDLPort(output, FPGATypes.PortDirection.Out));
}
// Inputs
foreach (string input in info.type.inputNames)
{
element.Containter.Add(MakeXDLPort(input, FPGATypes.PortDirection.In, info.type.inputsConstantValue));
}
// Get first encountered clb ?!
Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB));
Tile interconnect = FPGATypes.GetInterconnectTile(clb);
if (info.traverseBackwards)
{
TraverseBackwards(element, clb, interconnect, info);
}
foreach (string stopOverPortName in StopOverPorts)
{
element.AddPortToBlock(interconnect, new Port(stopOverPortName));
}
return(element);
}
protected override void DoCommandAction()
{
LibraryElement libEl = Objects.Library.Instance.GetElement(LibraryElementName);
List <Tile> anchors = new List <Tile>();
foreach (Tile placePos in TileSelectionManager.Instance.GetSelectedTiles().Where(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB)))
{
StringBuilder errorList = null;
bool placementOk = DesignRuleChecker.CheckLibraryElementPlacement(placePos, libEl, out errorList);
if (placementOk)
{
anchors.Add(placePos);
}
}
foreach (Tile t in anchors)
{
OutputManager.WriteOutput("Libary element " + libEl.Name + " can be placed at " + t.Location);
}
}
private void AddVivadoInstantiation(Tile t)
{
LibraryElement libElement = Objects.Library.Instance.GetElement(LibraryElementName);
if (libElement.VivadoConnectionPrimitive)
{
// bei Vivado 4 LUT6-Instanzen erstellen, eine mit Inputs und Output, drei davon dann nur mit Output
// only VivaodConnection primitves contains SubElements
bool checkResources = true;
foreach (LibraryElement other in libElement.SubElements)
{
LibElemInst instance = new LibElemInst();
instance.AnchorLocation = t.Location;
instance.InstanceName = GetNextInstanceName();
instance.LibraryElementName = other.Name;
instance.SliceNumber = SliceNumber;
instance.SliceName = t.Slices[(int)SliceNumber].SliceName;
LibraryElementInstanceManager.Instance.Add(instance);
ExcludeInstantiationSourcesFromBlocking markSrc = new ExcludeInstantiationSourcesFromBlocking();
markSrc.AnchorLocation = t.Location;
markSrc.LibraryElementName = other.Name;
markSrc.CheckResources = checkResources;
// mark source as blocked, only check onces
checkResources = false;
CommandExecuter.Instance.Execute(markSrc);
SaveLibraryElementInstantiation saveCmd = new SaveLibraryElementInstantiation();
saveCmd.AddDesignConfig = false;
saveCmd.InsertPrefix = true;
saveCmd.InstanceName = instance.InstanceName;
saveCmd.NetlistContainerName = NetlistContainerName;
CommandExecuter.Instance.Execute(saveCmd);
}
}
else
{
// for normal moduleas use ISE code
AddISEInstantiation(t);
}
}
protected override void DoCommandAction()
{
OutputManager.WriteOutput("# e.g. expect outpin left_3 SLICE_X5Y83 CMUX static_to_partial 5 -> expect vector index 5 in netname");
OutputManager.WriteOutput("# e.g. expect outpin left_5 SLICE_X342Y283 AMUX static_to_partial x -> no vector");
foreach (LibElemInst inst in LibraryElementInstanceManager.Instance.GetAllInstantiations().Where(i => Regex.IsMatch(i.InstanceName, InstantiationFilter)))
{
LibraryElement libElement = Objects.Library.Instance.GetElement(inst.LibraryElementName);
OutputManager.WriteOutput("# expected ports for instance " + inst.InstanceName + " (instance of " + libElement.Name + ")");
foreach (XDLPort port in libElement.Containter.Ports)
{
// only consider external ports
bool hasKindMapping = inst.PortMapper.HasKindMapping(port.ExternalName);
if (hasKindMapping)
{
PortMapper.MappingKind mappingKind = inst.PortMapper.GetMapping(port.ExternalName);
if (mappingKind != PortMapper.MappingKind.External)
{
continue;
}
}
bool hasMapping = inst.PortMapper.HasSignalMapping(port.ExternalName);
string inoutPin = port.Direction == FPGA.FPGATypes.PortDirection.In ? "inpin" : "outpin";
string portName = hasMapping ? inst.PortMapper.GetSignalName(port.ExternalName) : "unknown";
string index = inst.PortMapper.HasIndex(port.ExternalName) ? inst.PortMapper.GetIndex(port.ExternalName).ToString() : "-1";
if (portName.Equals("1"))
{
index = "0";
}
string line = "expect " + inoutPin + " " + inst.InstanceName + " " + inst.SliceName + " " + port.SlicePort + " " + portName + " " + index;
OutputManager.WriteOutput(line);
}
}
}
protected override void DoCommandAction()
{
// UCF/TCL location constraints
foreach (LibElemInst inst in LibraryElementInstanceManager.Instance.GetAllInstantiations().Where(i => Regex.IsMatch(i.InstanceName, InstantiationFilter)))
{
LibraryElement libEl = Objects.Library.Instance.GetElement(inst.LibraryElementName);
PrintLocationConstraint getLoc = new PrintLocationConstraint();
getLoc.Location = inst.AnchorLocation;
getLoc.SliceNumber = inst.SliceNumber;
getLoc.InstanceName = HierarchyPrefix + inst.InstanceName;
getLoc.BEL = libEl.BEL;
getLoc.Mute = Mute;
CommandExecuter.Instance.Execute(getLoc);
// copy output
if (getLoc.OutputManager.HasUCFOutput)
{
OutputManager.WriteWrapperOutput(getLoc.OutputManager.GetUCFOuput());
}
}
}
protected sealed override void DoCommandAction()
{
VHDLFile vhdlFile = new VHDLFile(EntityName);
InstantiationFilter = Regex.Replace(InstantiationFilter, "\\\"", "");
foreach (LibElemInst inst in LibraryElementInstanceManager.Instance.GetAllInstantiations().Where(i => Regex.IsMatch(i.InstanceName, InstantiationFilter)))
{
LibraryElement libElement = Objects.Library.Instance.GetElement(inst.LibraryElementName);
// add each component once
if (!vhdlFile.HasComponent(libElement.PrimitiveName))
{
vhdlFile.Add(new VHDLComponent(libElement));
}
vhdlFile.Add(new VHDLInstantiation(vhdlFile, inst, libElement, this));
}
// call base class implementation
PrintVHDLCode(vhdlFile);
}
private void RelocateInstancesForTCL(LibraryElement libElement, Tile anchorCLB, TCLContainer netlistContainer)
{
foreach (Tuple <Instance, Tile> tileSliceTupel in libElement.GetInstanceTiles(anchorCLB, libElement))
{
TCLInstance newInstance = new TCLInstance((TCLInstance)tileSliceTupel.Item1);
// change LOC property and the other fields carries out the actual relocation
Slice targetSlice = tileSliceTupel.Item2.Slices[(int)newInstance.SliceNumber];
newInstance.Properties.SetProperty("LOC", targetSlice.SliceName, false);
if (InsertPrefix)
{
newInstance.Name = InstanceName + "_" + newInstance.Name; // do not use / to avoid creating a new hierarchy for which w do not have a refernce cell
}
newInstance.SliceName = targetSlice.SliceName;
newInstance.SliceType = targetSlice.SliceType;
newInstance.SliceNumber = targetSlice.ContainingTile.GetSliceNumberByName(targetSlice.SliceName);
newInstance.TileKey = targetSlice.ContainingTile.TileKey;
newInstance.Location = targetSlice.ContainingTile.Location;
newInstance.LocationX = targetSlice.ContainingTile.LocationX;
newInstance.LocationY = targetSlice.ContainingTile.LocationY;
newInstance.OmitPlaceCommand = true; // TODO we only support GND primitves, overwork this when placing module
netlistContainer.Add(newInstance);
}
}
private bool ValidatePropertiesWithCallBack(LibraryElement libraryElement)
{
var isHasEmptyMandatoryProperty = libraryElement
.GetType()
.GetProperties()
.Any(property =>
property.CustomAttributes.Any(attribute => attribute.AttributeType == typeof(MandatoryAttribute)) &&
IsTypeEqualDefault(property.GetValue(libraryElement), property.PropertyType));
try
{
if (isHasEmptyMandatoryProperty)
{
throw new NullReferenceException("Element can't be null");
}
}
catch (Exception ex)
{
Console.WriteLine(ex.Message);
return(false);
}
return(true);
}
